http://www.theinquirer.net/default.aspx?article=36003. ;)
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How unprofessional. :stick:Quote:
AMD's Altair FX is a 6MB SOI 65 nanometre thingie
i really do wonder how this look against the competition.
from past experience, cache increases don't make a cpu go from fast to insane, so im not holding out for a godly cpu due to a cache bump.
Turtle 1 can you please stop posting from theInquirer please, and rather look around for some trusted sources like others do!:stick:
each CPU has 2MB, and total 4MB, so that means 2 CPU, and i assume by using the word "CPU" hes talking about cores.. Altaire is dual core?? i thought its quad core??Quote:
It will work at 2.7 to 2.9GHz and will end up with 2MB of dedicated L2 cache memory and an additional 2MB of shared L3 cache memory. When we say dedicated, it means that each CPU has 2 MB of L2 memory, total of 4MB of L2 memory plus 2MB of shared L3
Quote:
Originally Posted by Teroedni
Like the Vr-zone no doubt.;)
I think that Fudo has misunderstood something!
First he wrote:
“We managed to dig out a few more details about the real Quad core codenamed Altair FX”
So it’s a QC, he’s talking about!
Then he goes:
“When we say dedicated, it means that each CPU has 2 MB of L2 memory, total of 4MB of L2 memory plus 2MB of shared L3.”
So, with his math each core has 2 megs of L2! Four times of 2MB is 8MB+2MB of L2 equal 10 MB!!
Yeah Is The Inquirer at it best
And when it comes to Fudo
After all his Ati talks:stick:
And Turtle 1
Everything is better than the Inquirer;)
tahts what i said in post #4 ....Quote:
Originally Posted by Nedjo
according to him if "CPU" means "Cores" then yes K8L or the Altaire only has 2 cores ... i am guessing inquirer is bsing again
Ya I thought it was quad core also . he says it is in the link. so 1 cpu would have 8 mb of cache L2 and 2mb of L3 shared cache. I am having a hard time figuring out what the reporter is reportingQuote:
Originally Posted by theteamaqua
I think its L2 cache 2mb 4x2=8mb not shared.
L3 cache 512 4x512 = 2mb shared cache. I thought it was 4mb of shared L3 cache
I think he doesn't know what he is talking about and its what AMD has been saying it would be all along, each core with 1MB L2 (so 4MB total unshared), then All 4 share a 2MB L3.
Get a grip INQ.
Each core has 512KB of L2 (dedicated) and all 4 cores share the 2MBs of L3 cache.So Fudo mixed some things up(again...).
Also,each core has ( presumably ) 64KB L1D and 64KB L1I cache, although i have seen reports of 32+32 KB combination.
And need I say cache is only ONE of the arch. changes coming with the New Core.As some AMD exec already said :"There is no part of the chip that was left untouched".
So i believe we'll see some significant IPC advances with the new core.
And yes,the L3 cache size is subject to changes since AMD wants to differentiate it's offerings more with the coming New Core Gen.
Yeah my bad, it was 512kb
perhaps then what the INQ is trying to say is that they will make each core 1MB???
I don't think it's impossible that AMD may produce the variant of the QC part with 1MB dedicated L2 per core,but i think they evalueted pros and cons and are aiming for the best perf./$ option.Maybe for the server market ,highest number part will have larger L2.
With new IMC and high speed DDR2 next year,i think the New Core will do great against intel York/Wolf variants(i really believe c2d wouldn't be a match for it-for Dual Core part that is;Kents will have a hard time too since the shared FSB)
remember amd not contracts out some of their chips.
and i think it is 6mb total.
1mb per core L2, 2mbL3 shared.
If it does have 6MB cache, my moneys on 4x512k L2 + 4M L3.
Having total l3 equal total l2 would be bad enough, but having more l2 than l3 would be retarded (I know AMD's cache scheme is not inclusive, but the speeds are still tiered - so more 'faster' L2 would be prefered, so 4x1m l2 would be better than 4x512 + 2mb l3 where all cores are in use (if a single core uses all l3 then obviously that may be different).
However, if amd are using the l3 just to store the data that would be worked on by multiple cores, so each l2 stores the data that the core works on, and the l3 is used to ease intercore communication - not boost single core performance, then 4x1m + 2m l3 would be the better option - even though the 'shared cache' wouldn't boost performance when only one core is in use.
CharlieD has a new rant about intel and he basicaly said that Yorktown(or yorkfield) was just a rumour and no native quad core till nehalem.
So we will have AMD's New Core pitted against the just die shrinked Conroe with some new SSE additions and lower TDP from 65W to 50W (from Charlie's source).
Now without native QC and CSI ,intel seems in a bit of a trouble for late 07 early 08 since they would have "only" shrinked Conroes with SSE4 on the 1333MHz FSB.For the 4 core chip,it could be a bottleneck(we know that 1066 is).
Quote:
Originally Posted by CharlieD
intels 45nm chips will also be clocked higher. Current 65nm chips could easily be released at faster speeds, so even if 45nm only yields a minor increase in clocks a yorkfied at 3.6-4 ghz should still dominate k8l in most applications.
Remember AMD will have scaling issues as well - they'll have 4 cpus on a dual channel memory controller, and whilst the bottleneck will nock be as significant as intels fsb bottleneck, it will come into play in application that are heavily multithreaded and crave bandwidth. In addition we have no idea on how K8L's IPC will compare to core2, and k8l will not have equal clocks to match intels 65nm chips, let alone their 45nm ones.
I would suspect k8l will be a very nice multi socket server chip, but on the desktop I see intel maintaining their lead.
intels 45nm chips will also be clocked higher. Current 65nm chips could easily be released at faster speeds, so even if 45nm only yields a minor increase in clocks a yorkfied at 3.6-4 ghz should still dominate k8l in most applications.
Remember AMD will have scaling issues as well - they'll have 4 cpus on a dual channel memory controller, and whilst the bottleneck will nock be as significant as intels fsb bottleneck, it will come into play in application that are heavily multithreaded and crave bandwidth. In addition we have no idea on how K8L's IPC will compare to core2, and k8l will not have equal clocks to match intels 65nm chips, let alone their 45nm ones.
I would suspect k8l will be a very nice multi socket server chip, but on the desktop I see intel maintaining their lead.
Read again what i said.There seems to be no Yorkfield at all for 07(or in other words,no native QC chip till nehalem).
And how do you know AMD couldn't clock higher their Desktop variant of the New Core then "officialy stated in roadmaps" ??
By the H2 07' one should expect mature & additionaly tweaked 65nm process and higher clock speeds!That combined with new separate voltage management for IMC and the cores should bring much easier OCing then with K8s,bringing the maximum out of the new chips.
Yorkfield is on target - its the 45nm equivilent of kentsfield, a dual die MCM. The original roadmap and rumours claimed this, it was only recent speculation that there was going to be a 'native' quad core core 2 processor - which was just speculation.
If AMD's h2 2007 part were to outperform kentsfield, which will be clocked at 3ghz in the new year (333x9), and can already clock far higher they will have to either have higher IPC (very possible), or be clocked higher (doubtful). To outperform a higher clocked 45nm part they would have to have higher IPC and similar clock or significantly higher IPC and lower clock. All suggestions point to AMD having a significantly lower clock, but theres no indications on IPC. Judging by all indications given so far, it looks like k8l will perform clock for clock similar to core2 - but will be clocked slower - hence yorksfield will likely outperform K8L.
It didn't prevent you from posting it as news and funny you only thought of it after theteamaqua pointed it out :slap:Quote:
Originally Posted by Turtle 1
wait, as has been stated many times before, AMD's quad-cores will have 512kb L2 each core, plus 2mb shared L3, making 3mb cache, and being FX, that means 2 cpu's, for a total of 6mb
oops, first post upon waking up, math went out the window....lol
1mb per core would be neat tho
read the AMD tech docs. 512kb of L2 cache per core, 4mb of L3.
that makes sense, if the dual-cores are gonna have 2mb shared L3, then the quads should have 4mb...of course, 4x1mb L2 + 4mb L3 would be fantastic....for that extra 1-3% performance gain, lolQuote:
Originally Posted by breakfromyou
I have not seen anything about k8l having a 4 channel memory controller, or 2 dual channel ones. From my understanding k8l will plug into s1207 boards that are wired for dual channel, and whilst it would be possible for channels to be disabled for this purpose, it doesn't suggest there would be 4 channels, thus I'd put forward that there is a dual channel memory controller until proven otherwise.
Secondly where are these IPC numbers coming from? We don't know how much faster k8l will be clock for clock.
It seems almost definate that k8l will be a 4 issue design, so theres up to 33% improvement from that alone. I'm willing to bet there going to be some other small changes as well, but improving IPC is not something that you can do easily, and its not a task that scales linearly with the number of transistors your able to throw at the task. Taking into consideration your suggestion of20% higher IPC than kentsfield (which is optimistic):
3000 x 1.2 = 3600
If k8l was 20% faster clock for clock, it would take a 3.6ghz kentsfield to match a 3ghz k8l. AMD are aiming at 2.7-2.9ghz and traditionally amd don't leave much headroom on their high end parts.
You could buy a kentsfield today, overclock it and get k8l level performance. A year from now intels offering will have larger cache and faster fsb to keep the core fed, have a new chipset with a ddr3 memory controller, and possiby higher IPC with things like sse4 added to potentially speed thing up further.
I think the two will be very close on IPC, not a 20% difference at least, and intel will be clocked at least 20% higher stock, and have more headroom for overclocking.
Quote:
Originally Posted by informal
I also think the new core will do great... I also think AMD isnt afraid to let Intel have the lead for awhile. Intel is in a race... AMD is just trying to make a great processor.
~Mike
I don't think so.. AMD is still growing, Intel has already grown. I also dont think AMD cares if Intel is ahead. Time will tell ofcourse. :-)Quote:
Originally Posted by brentpresley
~Mike
Um, is the answer half its l2 cache?(1 core accessing 4mb as opposed to 4 cores on 2 dies accessing on average 2mb each). The conroe dies shared l2 allows the full 4mb to be given to one core, so you could say its a gain of extra cache when using only 1core as opposed to a loss when multitasking, as a discrete l2 design wouldn't allow the core to get the extra cache. When running 4 apps its not neccesarily the fsb that proves the bottleneck. 50% extra cache for the 45nm core 2 variants should help out on this score.Quote:
Originally Posted by LOE
As far as i know K8L will have 25% faster IPC that Core 2 Duo. It all will dependo on how high AMD can clock them
I don't know about the other points, but you're obviously misinformed about the definition of IPC. IPC stands for "instructions per clock", meaning the average amount of instructions a processor can complete every clock cycle. Therefore, IPC is independent of the clock cycle. Anyways, given the improvements, a best-case 40% IPC improvement over K8 is not unreasonable at all.Quote:
Originally Posted by brentpresley
i think that core will be 4*1MB L2 + 2MB L3. It will start in Q3 one Quad father. on L1FX+ with HT3, and DDR2@1066
AMD will release Barcelona first in H1 ( AMD press service told me ). Barcelona is for 1207, and AMD will release special Barcelona for Quad father. 4*512MB L2 + 2MB L3.
Don't cry because we can't use HT3 @ start. HT3 i very useless for moment HT2 for moment is not used to the maximum.
Next chipset's will be more higher clocked for HT2 i think. Ati can release very easely one chipset @ 1.5ghz even more.
I recommand to all who are waiting for a great product from AMD, to buy the X4 @ lunch and wait for DDR3 before any change.
Remember that HT3 is very useless for moment.
IMO....
If intel has the lead for awhile, so be it. I've never had a top of the line CPU so I don't really care much. AMD makes plenty fast CPUs for most things now, and if K8L is that much faster than K8 it will be awesome. Just because intel's chips may do better in benchmarks doesn't mean there will be that much difference in real life usage. Only purpose of those better benchmarks are for bragging rights ;)
My :2cents:
I got this at the inquirer also. Read it there is one statement that got my att. See if it gets yours. Because of that statement. K8L has to be a 4 issue core. Or the afore mentioned statement is completely false. I don't know if true or false. Only that its very interesting.
http://www.theinquirer.net/default.aspx?article=36017
As for Yorkfield being native or not. I believe the other reports that are out . Which all stem from IDF or the same timeframe. NO eirlier or latter sources. York will have Shared L2 cache among all 4 cores. If that = Native it will be native . If that = something else thats what it will be. If all the reports are correct about york . the best we will see is a 10% improvement in performance.Clock for clock
If Inquirer got it right on this link . York will be slower than K8L. I personnlly don't care which it is. I am more interested in who is putting out the more informed info. So we all can recognize and expuse more aeg members.
ok the info i got long time ago is mostly:Quote:
Originally Posted by brentpresley
that k8l will have 2x256kbit FPUs
but real k8l (at that time only one k8l existed)
Ya that was the one . . What is that 300% improvement over k8. I would think that 4 issue core would be required or it would be bottlenecked.Quote:
Originally Posted by brentpresley
uh, if you double the number of cores, the IPC should also double, aight?Quote:
Originally Posted by Shadowmage
and if you are talking about K8 vs K8L cores, 40% IPC improvement is not unreasonable but still pretty far fetched.
Quote:
Originally Posted by brentpresley
Don't think so. The number of decoder is not the number of issue that i heard.
AMD X4 will have four complexe decoder, easy to see it on die shot, even on the low res die shot.
I think that the number of fetch, is the number of issue. AMD don't go to 4 fetch, but the fetch will be 32bits instead of 16 bit of deep.
AMD may transphorm some simple instructions in one complexe. I think so. If any body have some news more fresh :stick:
thx
wait :slobber: & see :clap:
This is from the articleQuote:
Originally Posted by brentpresley
It also supports dual 128-bit SSE date flow, dual 128 bit load per cycle,
What does k8 have. 64-bit SSE date flow. If this info is correct thats a 300% improvement.
You would need "double Fetch" which K8L just happens to have
not a 4th integer stage
while reading the posts I was hoping somehow not to see C2D named.. but this time is not an exception.. :clap:
INQ is like broken phone. Collects pieces of rumors and puts all together. :nono:
what about integer in X4 ? I don't read anything about the question :stick:
K8L has 3 complex integer, in contrast to Conroe's ONE complex integer unit
Or even creates the rumor itself.Quote:
Originally Posted by BlackX
It should be forbidden to link to the Inquirer.
At least half of what them post is bull:banana::banana::banana::banana:.
But then Turtle 1 would perhaps have to little to do:lol:
This thread is about the amont of cache on K8L.
AMD's own words on this is 4x512kB L2 and 2MB L3 cache that is expandable, Maybe 3MB, 4MB .....
This is primarily because AMD knows quite well that cache increase gains very little for K8 architecture. Sempron with 256kb L2 are doing well against FX with just as little as 100- 150MHz clock differential.
The anandtech article linked by brentpresley explain most of the needed improvements for K8--> K8L to be more competitive.
It's quite amusing to see people counting their eggs about what K8L will do. Some said 25% higher IPC, some even say 40 + 40 + 20 which is rather silly.
The truth is that AMD will continue to perfom simulation about the expected performance of K8L on paper design, but usually, the tape out product will give a completely diffent result. Therefore any IPC improvement over K8 now is pure speculation at best.
While I would prefer to restrain myself from mentioning anything about Core 2, but I felt it would be rather boring not to do so.
Core 2 architecture for now we know and can buy the product on the open market. Intel actually restrained themselves from predicting what IPC improvement we would get until the product was finished and tested.
All these K8L IPC speculations are pure marketing propanganda and BS to keep AMD customers, especially the server ones happy and hopefull.
The truth is that, K8L or whatever it will be called is still going to be 3 issue Core with a lot of core improvement. This will not change things drastically against Core 2 archtecture that have potential clock headroom aside from boosting a strong OoO execution units, aggresive prefetching and huge cache estate.
Thanks to brentpresley for pointing out the FSB issue with kentsfield. Yes,It's true that Core 2 architecture max out at about 3.4-3.5GHz on the FSB. That's alot of headroom for Intel before DDR3. Core 2 prefecthers are very aggressive and therefore have little use for an on-die memory controller. An on-die MC on Core 2 will be an added bonus, but not anything to be eager about.
There are still quite a lot of tweaking that Intel is doing on the Core 2 architecture and that should make AMD be aware that they have a long way to go.
EDIT: For spelling
:D :D :D that is like 130392920% improovement :toast:Quote:
Originally Posted by agenda2005
NN you know full well that comment . Would raise a few eyebrows. You must be a good fisherman.;)Quote:
Originally Posted by nn_step
Another FUD spreaded by Fuad :D
Common, die shoot of K8L/K10 shows that each core L2 cache is surrounded by logic, so AMD can't do anything with it. The only cache which can be expanded is L3 and even AMD is stating clearly in leaked documents about that. So this 'news' is FUD or he mixed L2 with L3 cache:rolleyes: .
You can speculate whatever you like, but making up for 20% lag is quite a lot in the CPU world.Quote:
Originally Posted by metro.cl
Time will tell, but your 25% IPC improvement of K8L over Conroe is too ambitious IMHO. That is approximately 45% improvement per clock over K8. AMD will have to come out with a perfect design that will fill up the CPU pipeline and extensively utilize the 3 wide issue.
Even Core 2 with its OoO and aggresive prefetchers is only able to sustain one issue per clock cycle. Aside from that Core 2 also have potentially higher clock to execute instructions.
Go and read up man. AMD have their work cut out for them.
Acually since 3 this morning I have read a lot. Visted my favorite forum. Assembled to C2D water cooled gamers. Installed software. prepared for shipping. So all and all been pretty busy this day.Quote:
Originally Posted by Teroedni
ugh.... just..Quote:
Originally Posted by Turtle 1
seriously :/
so what did you spend the other 23 hours for then? :rolleyes:Quote:
Originally Posted by Turtle 1
What, would you like a trophy or something?Quote:
Originally Posted by Turtle 1
Also i was kidding couse you put 4x512MB no 4x512kb as it should beQuote:
Originally Posted by agenda2005
do you know how much ipc improoved from p4 to c2d?
why cant amd improove 25%? time will tell im not making up i got this info from the same person that told me 9 months before that:
C2D would kill amd
C2D would have cold bug
C2D would get over 3.6GHz OC
so i trust him
lol i dont have such good friends as to see things but i get info from some of them :DQuote:
Originally Posted by brentpresley
lets debate that is the nice thing in forums i learn a lot from you guys i got into this world about 1.5 years ago only
they do with ln2 :)Quote:
Originally Posted by brentpresley
Any of your friends, metro.cl, saw Brisbane CPU in action?? Mayby you saw die shot accidentally? Any info will be welcome :D .
one of them has one, i've been asking for a pic and some action to show, but they are playing with something else, he promised late November for a SS or some info of it.Quote:
Originally Posted by Lightman
But so far it is just AM2 in 65nm
THANKS for this info :D :toast: :toast:Quote:
Originally Posted by metro.cl
BTW keep asking him for pictures and mayby some OC session.
PS. If I may ask, with what they are playing right now??
yeah didn't you know?Quote:
Originally Posted by brentpresley
lol i dunno, but they got brisbane & 4300 and they wont play with any of them, so it must be something goodQuote:
Originally Posted by Lightman
tryed getting one from them but was a no go also :(
Breaks bring browser to screaming hault. User screams LINK PLEASE!!!!!Quote:
Originally Posted by metro.cl
Just ask few guys here who use LN2 ;)Quote:
Originally Posted by Turtle 1
the should be 4xcores with 1MB L2 each and 2MB L3 :)
The stupid enquirer always come with something out to make the news to overflow.
I wonder what they will win with all this:slapass:
By the way, if this is true I can't see it having 6 mb of cache.
Man cooper I read almost every thread here and I have not once seen A report of coldbug. This does not refer to the news thread its all threads in most catogories.Quote:
Originally Posted by Cooper
There isn`t any special "Conroe has cold bug" thread. And those certainly aren`t here in News section.
Enough with offtopic already. Threa is about AMD K8L - not the Conroe cold bug
Alright, thanks for the correction. I will wait and see what AMD can bring to the table.Quote:
Originally Posted by metro.cl
outch!!!! that makes these look pretty obsolete .......... amd will take a beating in 2007 big time it seemsQuote:
Originally Posted by brentpresley
ummm, a little secret for you. Normal number of Integer operations is under two at a time.Quote:
Originally Posted by dinos22
if you don't believe me. http://www.cpuid.com/perfmon.php
Use the log function and find out for yourself
it really is a pointless discussion without any benchmarks still so let's see what happens...........AMD is getting severely beaten at the moment. How long will we have to wait until a decent CPU for an extreme overclocker will come oneQuote:
Originally Posted by nn_step
umm if you didn't know the only weak point about AMD is the Floating point performance. Which from what we hear should be the new king
i think he is saying that AMD is about to correct Integer floating point performance in new CPUsQuote:
Originally Posted by brentpresley
let's wait and see i say :cool:
i'm going with whoever is fastest on the day. Right now Intel is a country mile ahead
http://www.amd.com/us-en/assets/cont...alystDayV2.pdf
there, take a look at that. im sure it would set a few of you clear on some info thats been going around at the inq :\
about my previous post, i said it was 4mb of L2 cache...i was wrong :( it says 2+ in the tech docs i just linked to. so it will be 4x512kb + 2+kb. so thats a total of 4mb...not too shabby. just keep the latency low, and it should be more than good enough.
i thought the 3/4 issue thing wasn't something to worry about? isn't it visible in the pictures of the core? eh, it better be 4. AMD did say that nothing about the K8 architecture went untouched. so...lets hope it really is a 4 issue core.
^^ Integer and FP operations are independent of each other. There's no such thing as "Integer floating point" operations.
nn_step: AMD's FPU was and still is one of the best on the market. All Intel did was add 2 more to make 3. It's ALU and memory performance is what's lacking. The memory controller does make up for some of the problems though.
When doing 2 threads at a time, IPC of the ENTIRE thing would double. AMD's referring to single thread performance, in which the number of cores does not matter (only makes things worse). Increasing the number of cores LOWERS IPC in single-threaded situations due to bus contention, cache coherency misses, etc.Quote:
Originally Posted by vitaminc
Plus, OoO loads itself adds 40% performance in some extremely limited situations (from Intel tech docs).
Your calculation is useless, because only 4 uop can be handled by the next stage of the pipeline (3 uops for K8 and probably for K8L). Core dosn't realy need more compex decoders, because most instructions can be handled by simple decoders. For example in Core SSE instructions are translated in one uop, whereas in K8 it needs 2 uops (because of 64-bit execution units).Quote:
Originally Posted by LOE
They means for two vector SSE2 instruction which can execute two 64-bit multiplications and two 64-bit additions in the same cycle. Core already can do it.Quote:
EDIT: Amd says up to 4 double precision flops per cycle - is this possible with only 3 complex decoders?
Apropos, what about anti-HT? Is it still not out yet? :D
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