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The numbers sure don't suggest otherwise. ;) they suggest 10% and 20% with turbo, certainly nothing groundbreaking. Oh right I forgot, they just have to turn some screws and it'll take right off lol :D. Maybe benchmarks using the AVX instructions will show a wider gap, but then again the competition is going to have the same instructions and more. Providing the benchmarks aren't rigged like sysmark, sisoft etc. of yesteryear that is.Quote:
Originally Posted by terrace215
1) 96% of optimizations possible are performed identically regardless of underlying processor architecture. An additional 3% are performed identically for all implementations of a given instruction set. Finally only 1% [which equates to less than 0.001% of total performance] are processor architecture specific.Quote:
Originally Posted by Calmatory
3) Given that AMD has MWAIT and MONITOR Direct pathed http://support.amd.com/us/Processor_...11_5-21-09.pdf It would suggest that they are of some use for AMD.
do you get paid by AMD?if not AMD should create a PR victims dept and pay you:rofl:Quote:
Originally Posted by flippin_waffles
was that really necessary? your post...(and this one as well lol). do not really add anything to the discussion, other than attacks and verbiage. yes FP was a little snippy, but at least he was on topic, he didnt really attack Terrance now did he?Quote:
Originally Posted by radaja
OMG43 it was in jest
.....i knew that...i was just playing with you.....:eek:Quote:
Originally Posted by radaja
I don't understand. If a processor supports an instruction set you shouldn't have to optimize specifically for it. It's supposed to be a black box, so long as you put in the right stuff as dictated by the set it outputs the right stuff.
That is assuming that an instruction set is static and unchanging.Quote:
Originally Posted by cegras
Additions such as new instructions or larger vector registers, can allow a new window to additional optimizations. However things such as clever compilers, sufficient registers, and OoO can eliminate any advantages such additions may have. For example a tight loop that walks down memory loads a word of data, operates on it and writes it back; which is identical to a tight loop that loads a chunk of words, operates on them, and writes them back.
Now in non-speculating Super-scalar hardware, every time a branch instruction it hit, the instruction issue must halt until the branch is known; which in vector code such branching happens less often.
However once you introduce branch prediction, provided that the scalar logic is equally broad as the vector logic. [Say operate on 4 words, thus 4 ALUs]; the performance difference disappears. Now if the vector logic is broader than the scalar logic, using vector instructions improves performance.
That xbitlabs article AMD Bulldozer Microprocessors May Not Bring Dramatic Performance Boosts is a joke. Anyone reading some forum could wrote it more correctly and with some level of interest ... ex. "the first Bulldozer micro-architecture desktop/workstation chip code-named Zambezi (which belongs to Orochi family, according to the firm) will feature eight x86 processing engines with a multithreading technology, two 128-bit FMAC floating point units, shared L2 cache, shared L3 cache as well as integrated memory controller. AMD also states that the new CPU will feature “extensive new power management innovations”."Quote:
Originally Posted by ajaidev
So he refers to Nov2009 slides and he didnt yet figure out that FMACs are two per module and not "two per core (x8)" or shared L2 cache will be shared a) between eight cores or b) between core and what. And as usual xbitlabs wrote (pump) that news at least 3rd-4th time since originally one on their site cover that matter (only if someone wish to count), and delivering nothing new or explanatory. As it seems xbitlabs also don't like to talk about unreleased products also.
I s understood that Magny-Cours is 2x 6-core die over one extra HT-link(featured since rev.RB-C2 aka. first "Shanghai" core) inside MCM. And i dont see that 125W TDP as bad thing or something AMD's constrained with. So there should be all perfect to slip new arch inside "previously set power bands". After all that's really feature they streaming at and where they see their competitiveness ;) And i believe 4P 75W ACP (125W TDP) cores inside one server rack unit (4U/5U) is pretty demanding to cool downQuote:
Originally Posted by informal
Ok All of us here know (expect) that Bobcats and Bulldozers should be greener than AMD logo or Evergreen line :D But you still avoid gave up some serious answers rather you stick to marketing PRQuote:
Originally Posted by JF-AMD
""""Quote:
Originally Posted by JF-AMD
It would be nice to know real perf numbers instead overhyped relative performance that is printed on all AMD 2011 posters. You could save a whale or two in meantime, instead of giving away Enron-like performance promises.
We never release perfromance benchmarks, pricing, clocks/cache info, launch date or other data prior to launch. When we do release performance prior to launch it is typically STREAM to show memory bandwidth. The performance gain is actually not "enron-like", it is completely reasonable.