:confused: :confused: :confused:Quote:
Originally Posted by atistatic
Welcome to the forums anyway :toast:
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:confused: :confused: :confused:Quote:
Originally Posted by atistatic
Welcome to the forums anyway :toast:
no. 4x4 is a socket setup. it'd be like all the comparisons of old, between AM2 and Conroe :lol2: :rofl:Quote:
Originally Posted by atistatic
high-res. new Opteron photo
http://i.n.com.com/i/ne/p/2006/amdbarcelona550x512.jpg
it looks like this will be the only x86 native quad-core for whole 2007
Yorkfield == 2xPenryn(45nm) unfortunately == kentsfield at high frequencies
will you look at those massively improved FP and integer units :slobber:
Not true . Yorksfield will be 12mb of shared cache . not 6mb per core.Quote:
Originally Posted by MAS
Also yorksfield is also reported to be native quad core. . You can get links in news section. Also You are forgetting the Intel is going to be using high K metal gates on the 45nm process. Which is 20%+ faster switching speed.And 5x less leakage. I will buy yorksfield over the 65nm old tech that AMD will offer. Since both new processors will arrive 3rd qt. 07 . Intel is out for blood. AMD should have never sued intel . As now the Dell is selling AMD cpu's they are unable to supply the maket with cpu's/ Intel wins the law suite/ Intel will lead in performance for at least the next 3 years.:toast:
This thread is about K8L, keep it to that. No need for another fanboyism thread here.
Don't worry,he'll do that again.He always does.Quote:
Originally Posted by v0dka
I second your proposal,let's keep this thread to what the thread title says.
Oh my! That K8L die photo looks even more powerful than the one posted back in May! C2Q doesn't stand a chance against that kind of processing power! :rolleyes:
Then is K8L or no ?Quote:
Originally Posted by ozzimark
http://theinquirer.net/default.aspx?article=35011
AMD LAID OUT a bit more about Barcelona today at MPF, focusing in on six areas. They talked about SSE128, enhanced IPC, efficient memory use, better caches, virtualization and power management.
In the macro sense of things, Intel is chasing AMD, but on the micro level, the opposite is true. The talk was given by Ben Sander of AMD, you can read it on his nametag if you don't believe me.
Barcelona is the first native quad-core AMD CPU, commonly but wrongly referred to as K8L. It is the first real new core from the chipmaker in quite a while, not merely a massaged version of what came before. You should be seeing it in Q2/07, although some whispers are now saying Q3.
Other than four cores, the most obvious difference is the new widened SSE instructions. On the pre-Barcelona parts, SSE was done in 64 bit chunks, so if you wanted to do a 128b operation, you needed two passes, possibly more. With the widening of SSE, it should immediately double throughput on SSE instructions. Obviously media operations will benefit, but HPC and FP heavy ops will get a solid kick in the pants too.
In addition to the obvious width change, several less noticeable changes were made to support it. Instruction fetch was upped from 16B/cycle to 32B and support for unaligned load ops was added and cache bandwidth was doubled to support this. Last but not least the FP scheduler was widened from 64 to 128b.
The enhanced IPC is more a case of little improvements adding up to a bigger bang rather than any single thing standing out. The SSE improvements add a bit here and there to start with, and a better branch predictor adds to this. It is bigger and better with a larger history, a dedicated 512 entry indirect predictor, and the return stack is doubled in size.
In the catching up with Intel side of things, added a sideband stack optimizer, out of order load execution and data dependent divide latency. They also upped the TLB to support 1G pages, 48-bit physical addressing, and improved the ITLB and DTLBs. There are also more fastpath instructions and a few more bit manipulation instructions and SSE extensions.
For RAM efficiency, one of the main things they did was make the two memory controllers on the chip act independently, up to Rev G they could only act in lockstep. This lets AMD hit two memory locations at once, potentially a big win for server type apps, but for single users, it's benefit is less clear.
On top of this, they changed the northbridge a lot increasing buffers and adding support for new DRAM types. The Barcelona controller will do FBD if necessary, but the chances of you seeing that are something less than zero. AMD also updated the way paging is done and modified the way write bursting happens.
Additionally, one of the big complaints I hear is prefetch, and that has been comprehensively addressed. They now track positive, negative and non-unit strides, and have a dedicated prefetch buffer. On top of that, Barcelona is much more aggressive in how they fill idle ram cycle and updated the core prefetchers on both the L1D and L1I side.
The newer L3 cache is called a 'victim cache', it sits on top of the existing discrete L2 caches, and is shared among the cores. The big thing here is that if the caches are empty, the request goes to L1 cache. If that fills, the data line is evicted to L2, and when L2 fills, it goes to L3. If a core reads from L3, there are one of two things that can happen. If it is data, the line is moved to L1D, but if it is instructions, the line may be moved to L1I, or it may be copied to L1I and left in L3. The L3 is not exclusive, and the point of this is that code is often shared among the cores while data is far less often. The cache lines have performance hints associated with them that will clue to cores in on the whole copy vs move debate.
That brings us to virtualization, a topic we have covered a lot in our Pacifica articles (1, 2, 3 and 4 )The main advance Barcelona brings is that it turns on Nested Page Table support and a few other things that did not make the cut on the Rev F parts. It is also said to reduce world switch time going to the hypervisor and back by 25%.
One of the last things they did was to break the CPU and northbridge into separate power planes. This will allow the CPUs to be clocked up and down, and volted up and down independently of the Northbridge. This was a major sticking point in the ramp of the previous iterations of the chip, and I expect big dividends here, and it also saves a lot of power. I am also told that they can change the voltage on cores independently, but that is more of a motherboard issue. Since it is not really supported anywhere on the current platforms, don't look for a BIOS option to turn it on, but if it came back in later platform revisions, I would not be overly surprised.
What you have for Barcelona is a CPU that looks a lot like the older revs at the block diagram level, but no part of it is untouched. Some pieces a massively updated, others far less so. In any case, it will add up to significant gains overall, but will it be enough to dethrone Woodcrest 2 core? Stay tuned in the middle of next year for the answer to that. µ
Kick ass...Quote:
One of the last things they did was to break the CPU and northbridge into separate power planes. This will allow the CPUs to be clocked up and down, and volted up and down independently of the Northbridge.
Ryan
Thanks for the info SunFlowerSeeds. Hopefully K8L will prove itself at launch, all while not emptying the consumer wallet.
It isn't performance I am worried about. It is the cost of the chip to the consumer. I'd bet that this chip will cost at least $500 for the lower-end one at launch.
From the Inq article one thing puzzles me : in their description there is no extra FPU , just the original 2 were extended from 64 to 128bit and can do one cycle SSE ops.
There will always be a low-end version to match C2D. Should not be a problem for overclockers. ;)
Quote:
Originally Posted by Darkenreaper57
Thank you for this GREAT info SunFlowerSeeds...:D
My respect to you..:toast:
My God! DFI get working on it and dont make us awit till whenever!Quote:
Originally Posted by SunFlowerSeeds
Quote:
Originally Posted by SunFlowerSeeds
Amd is the innovator. :)
Its not so much innovation as they keep finding ways to make features that are normally very expensive/difficult to implement in commodity hardware in a cheap and reliable fashion.
I wouldn't expect them to have independant core volts any time soon, if ever. AFAIK it requires having a seperate VRM for each core on the motherboard which would increase costs and pin counts dramatically (IOW they'd probably need a new socket...AM3+ maybe?).
Correction AM2+ is AM2 only with HT3.0. AM2+ cpus are backwords compatible aka K8L. There is no other socket.Quote:
Originally Posted by mesyn191
Fox of few words...
actually, word on the street is that K8L holds independent vcore for us. Do I have a link? No. I read it on the forums somewhere. Maybe someone else can produce a link.
Ryan
Don't know much about AMD aye? Can you say, embedded Silicon Germanium, with THEE Dual Stress Liner, and Stress Memorization technology. (Cu) (CMOS) on (SOI) wafers, with the use of dielectric constant gate K insulators on 65nm with considerably less leakage make K8L's FAB process far more superior then your fandom is thickheaded by 40%! (15% faster in process improvments including the 2x FPU, ALu, dual 128-bit SSE123 and SSE4a later, 256-bit cache, 128-bit wide points, 20% clock for clock, and 5% when adding clock boosts.) Thad be the magic 40% faster # we have a winner... Keep on topic, this is about K8L not the CON. :stick: Your not the only one who knows there shEtz wolf boy!Quote:
Originally Posted by Turtle 1
Fox of few words...
http://photos1.blogger.com/blogger/7...743DvWIml8.jpgQuote:
Originally Posted by IvanAndreevich
Never knew 3.5ghz with a 5.2GT's 2.6HT clock was so slowwww... at stock. :slap: Nobody wants to argue but the foxmister Yo! :rolleyes: Your clames are useless without links little boy. Prove K8L will be woobed by the CONiE, wellp we can't until it comes out but based on clock facts releaced by mobo manufax... we will have some killer speeds for CON to deal with. Clock for clock its 20% faster too. Just think how this baby will Over CCCCC! The F out of the CON booya.
Not for the forseeable future no, but AMD is supposed to have a AM3 socket of some sort around 2H 2008 (http://theinquirer.net/default.aspx?article=35211), there are of course no plans for a AM3+ but that was just my round about way of suggesting that a feature like variable volt. per core on one die are at best very far off for AMD.Quote:
Originally Posted by Grayfox84
Sounds like BS seeing as how AMD has already produced slides contrary to this.Quote:
Originally Posted by FghtinIrshNvrDi
http://www.hardocp.com/image.html?im...dfMV8zX2wuZ2lm
http://www.hardocp.com/image.html?im...dfMV80X2wuZ2lm
http://www.hardocp.com/image.html?im...dfMV81X2wuZ2lm
http://www.hardocp.com/image.html?im...dfMV82X2wuZ2lm
They intend to lower power consumption by lowering the clockspeed of the core but the voltage remains the same.
More info. here:
http://www.theinquirer.net/default.aspx?article=33887
grayfox: getting 403'd on your link