OCZ 3200EL plat rev 2

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10-06-2004, 08:04 AM
ugp

@Ubermann
Hey man want to have alittle contest?

Want to see who can get the most bandwidth out of stock speeds? (Being 200FSB)

If so feel free to copy and paste this as a template :p: :D

Since I am having trouble with OC I decided to start. I don't have anything to compare it to though...

Here is my results so far...

SiSoft Sandra Bandwidth: 3015MB/s
SiSoft Sandra Arithmetic: 9225 MIPS
SiSoft Sandra Multi-Media: 19,152 it/s
SuperPi: 44s

FSB BUS Frequency: 200
AGP BUS Frequency: 66
Clock Spred Spectrum:
LDT Downstream Width: AUTO
LDT Upstream Width: AUTO
LDT/FSB Frequency Ratio: AUTO
CPU/FSB Frequency Ratio: 10.0
CPU VID Control: 1.550V
CPU VID Special Control: AUTO
ChipSet Voltage Control: 1.6V
AGP Voltage Control: 1.5V
DRAM Voltage COntrol: 2.8V

DRAM Frequency Set (MHz): 200MHz 1:1
Command Per Clock (CPC): 1T
CAS Latency Control (TCL): 2
RAS# To CAS# Delay (TRCD): 2
Min RAS# Active Time (TRAS): 5
Row Precharge Time (TRP): 2
Row Cycle Time (TRC): AUTO
Row Refresh Cycle Time (TRFC): AUTO
Row To Row Delay (TRRD): AUTO
Write Recovery Time (TWR): AUTO
Write to Read Delay (TWTR): AUTO
Read To Write Delay (TWTR): AUTO
Refresh Period (TREF): AUTO
Write To CAS Latency (TWCL): AUTO

DQS Skew Control: AUTO
DQS Skew Value: AUTO
DRAM Drive Strength: AUTO
Max Async Latency: AUTO
Read Preamble Time: AUTO
Idle Cycle Limit: AUTO
Dynamic Counter: AUTO
R/W Queue Bypass: AUTO
Bypass Max: AUTO
32 Byte Granularity: AUTO

----------------------------------------------

SiSoft Sandra Bandwidth: 3015MB/s
SiSoft Sandra Arithmetic: 9219 MIPS
SiSoft Sandra Multi-Media: 19,152 it/s
SuperPi: 45s

FSB BUS Frequency: 200
AGP BUS Frequency: 66
Clock Spred Spectrum:
LDT Downstream Width: AUTO
LDT Upstream Width: AUTO
LDT/FSB Frequency Ratio: AUTO
CPU/FSB Frequency Ratio: 10.0
CPU VID Control: 1.550V
CPU VID Special Control: AUTO
ChipSet Voltage Control: 1.6V
AGP Voltage Control: 1.5V
DRAM Voltage COntrol: 2.8V

DRAM Frequency Set (MHz): 200MHz 1:1
Command Per Clock (CPC): 1T
CAS Latency Control (TCL): 2
RAS# To CAS# Delay (TRCD): 2
Min RAS# Active Time (TRAS): 10
Row Precharge Time (TRP): 2
Row Cycle Time (TRC): AUTO
Row Refresh Cycle Time (TRFC): AUTO
Row To Row Delay (TRRD): AUTO
Write Recovery Time (TWR): AUTO
Write to Read Delay (TWTR): AUTO
Read To Write Delay (TWTR): AUTO
Refresh Period (TREF): AUTO
Write To CAS Latency (TWCL): AUTO

DQS Skew Control: AUTO
DQS Skew Value: AUTO
DRAM Drive Strength: AUTO
Max Async Latency: AUTO
Read Preamble Time: AUTO
Idle Cycle Limit: AUTO
Dynamic Counter: AUTO
R/W Queue Bypass: AUTO
Bypass Max: AUTO
32 Byte Granularity: AUTO

----------------------------------------------

SiSoft Sandra Bandwidth: 3013MB/s
SiSoft Sandra Arithmetic: 9225 MIPS
SiSoft Sandra Multi-Media: 19,149 it/s
SuperPi: 45s

FSB BUS Frequency: 200
AGP BUS Frequency: 66
Clock Spred Spectrum:
LDT Downstream Width: AUTO
LDT Upstream Width: AUTO
LDT/FSB Frequency Ratio: AUTO
CPU/FSB Frequency Ratio: 10.0
CPU VID Control: 1.550V
CPU VID Special Control: AUTO
ChipSet Voltage Control: 1.6V
AGP Voltage Control: 1.5V
DRAM Voltage COntrol: 2.8V

DRAM Frequency Set (MHz): 200MHz 1:1
Command Per Clock (CPC): 1T
CAS Latency Control (TCL): 2
RAS# To CAS# Delay (TRCD): 2
Min RAS# Active Time (TRAS): 5
Row Precharge Time (TRP): 2
Row Cycle Time (TRC): AUTO
Row Refresh Cycle Time (TRFC): AUTO
Row To Row Delay (TRRD): AUTO
Write Recovery Time (TWR): AUTO
Write to Read Delay (TWTR): AUTO
Read To Write Delay (TWTR): AUTO
Refresh Period (TREF): AUTO
Write To CAS Latency (TWCL): AUTO

DQS Skew Control: Increase
DQS Skew Value: 64
DRAM Drive Strength: AUTO
Max Async Latency: AUTO
Read Preamble Time: AUTO
Idle Cycle Limit: AUTO
Dynamic Counter: AUTO
R/W Queue Bypass: AUTO
Bypass Max: AUTO
32 Byte Granularity: AUTO

----------------------------------------------

SiSoft Sandra Bandwidth: 3020MB/s
SiSoft Sandra Arithmetic: 9225 MIPS
SiSoft Sandra Multi-Media: 19,149 it/s
SuperPi: 45s

FSB BUS Frequency: 200
AGP BUS Frequency: 66
Clock Spred Spectrum:
LDT Downstream Width: AUTO
LDT Upstream Width: AUTO
LDT/FSB Frequency Ratio: AUTO
CPU/FSB Frequency Ratio: 10.0
CPU VID Control: 1.550V
CPU VID Special Control: AUTO
ChipSet Voltage Control: 1.6V
AGP Voltage Control: 1.5V
DRAM Voltage COntrol: 2.8V

DRAM Frequency Set (MHz): 200MHz 1:1
Command Per Clock (CPC): 1T
CAS Latency Control (TCL): 2
RAS# To CAS# Delay (TRCD): 2
Min RAS# Active Time (TRAS): 5
Row Precharge Time (TRP): 2
Row Cycle Time (TRC): AUTO
Row Refresh Cycle Time (TRFC): AUTO
Row To Row Delay (TRRD): AUTO
Write Recovery Time (TWR): AUTO
Write to Read Delay (TWTR): AUTO
Read To Write Delay (TWTR): AUTO
Refresh Period (TREF): AUTO
Write To CAS Latency (TWCL): AUTO

DQS Skew Control: AUTO
DQS Skew Value: AUTO
DRAM Drive Strength: AUTO
Max Async Latency: 08.0
Read Preamble Time: AUTO
Idle Cycle Limit: AUTO
Dynamic Counter: AUTO
R/W Queue Bypass: AUTO
Bypass Max: AUTO
32 Byte Granularity: AUTO

----------------------------------------------

SiSoft Sandra Bandwidth: 3017MB/s
SiSoft Sandra Arithmetic: 9225 MIPS
SiSoft Sandra Multi-Media: 19,151 it/s
SuperPi: 44s

FSB BUS Frequency: 200
AGP BUS Frequency: 66
Clock Spred Spectrum:
LDT Downstream Width: AUTO
LDT Upstream Width: AUTO
LDT/FSB Frequency Ratio: AUTO
CPU/FSB Frequency Ratio: 10.0
CPU VID Control: 1.550V
CPU VID Special Control: AUTO
ChipSet Voltage Control: 1.6V
AGP Voltage Control: 1.5V
DRAM Voltage COntrol: 2.8V

DRAM Frequency Set (MHz): 200MHz 1:1
Command Per Clock (CPC): 1T
CAS Latency Control (TCL): 2
RAS# To CAS# Delay (TRCD): 2
Min RAS# Active Time (TRAS): 5
Row Precharge Time (TRP): 2
Row Cycle Time (TRC): AUTO
Row Refresh Cycle Time (TRFC): AUTO
Row To Row Delay (TRRD): AUTO
Write Recovery Time (TWR): AUTO
Write to Read Delay (TWTR): AUTO
Read To Write Delay (TWTR): AUTO
Refresh Period (TREF): AUTO
Write To CAS Latency (TWCL): 5

DQS Skew Control: AUTO
DQS Skew Value: AUTO
DRAM Drive Strength: AUTO
Max Async Latency: AUTO
Read Preamble Time: AUTO
Idle Cycle Limit: AUTO
Dynamic Counter: AUTO
R/W Queue Bypass: AUTO
Bypass Max: AUTO
32 Byte Granularity: DISABLED
10-06-2004, 08:08 AM
Ubermann

Working on making a "manual" for bios settings, taking selected info from
http://www.adriansrojakpot.com/Speed...uide_Index.htm
(hope they dont mind)

1. Command per clock
Common Options : Enabled, Disabled, Auto
Quick Review
This BIOS feature allows you to select the delay between the assertion of the Chip Select signal till the time the memory controller starts sending commands to the memory bank. The lower the value, the sooner the memory controller can send commands out to the activated memory bank.
When this feature is enabled, the memory controller will only insert a command delay of only one clock cycle or 1T.
When this feature is enabled, the memory controller will insert a command delay of two clock cycles or 2T.
The Auto option allows the memory controller to use the memory module's SPD value for command delay.
If the SDRAM command delay is too long, it can reduce performance by unnecessarily preventing the memory controller from issuing the commands sooner.
However, if the SDRAM command delay is too short, the memory controller may not be able to translate the addresses in time and the "bad commands" that result will cause data loss and corruption.
It is recommended that you try enabling SDRAM 1T Command Control for better memory performance. But if you face stability issues, disable this BIOS feature.

2. CAS Latency Time
Common Options : 2, 3 (SDR memory) or 1.5, 2, 2.5, 3 (DDR memory)
Quick Review
This BIOS feature controls the delay (in clock cycles) between the assertion of the CAS signal and the availability of the data from the target memory cell. It also determines the number of clock cycles required for the completion of the first part of a burst transfer. In other words, the lower the CAS latency, the faster memory reads or writes can occur.
Please note that some memory modules may not be able to handle the lower latency and may lose data. Therefore, while it is recommended that you reduce the SDRAM CAS Latency Time to 2 or 2.5 clock cycles for better memory performance, you should increase it if your system becomes unstable.
Interestingly, increasing the CAS latency time will often allow the memory module to run at a higher clock speed. So, if you hit a snag while overclocking your SDRAM modules, try increasing the CAS latency time.

3. RAS-to-CAS Delay
Common Options : 2, 3, 4
Quick Review
This BIOS feature allows you to set the delay between the RAS and CAS signals. The appropriate delay for your memory module is reflected in its rated timings. In JEDEC specifications, it is the second number in the three or four number sequence.
Because this delay occurs whenever the row is refreshed or a new row is activated, reducing the delay improves performance. Therefore, it is recommended that you reduce the delay to 3 or 2 for better memory performance.
Please note that if you use a value that is too low for your memory module, this can cause the system to be unstable. If your system becomes unstable after you reduce the RAS-to-CAS delay, you should increase the delay or reset it to the rated delay.
Interestingly, increasing the RAS-to-CAS delay may allow the memory module to run at a higher clock speed. So, if you hit a snag while overclocking your SDRAM modules, you can try increasing the RAS-to-CAS delay.

4. Min RAS# active time
Common Options : 4, 5, 6, 7, 8, 9
Quick Review
Like DRAM Act to PreChrg CMD, this BIOS feature controls the memory bank's minimum row active time (tRAS). This constitutes the time when a row is activated until the time the same row can be deactivated.
If the tRAS period is too long, it can reduce performance by unnecessarily delaying the deactivation of active rows. Reducing the tRAS period allows the active row to be deactivated earlier.
However, if the tRAS period is too short, there may not be enough time to complete a burst transfer. This reduces performance and data may be lost or corrupted.
For optimal performance, use the lowest value you can. Usually, this should be CAS latency + tRCD + 2 clock cycles. For example, if you set the CAS latency to 2 clock cycles and the tRCD to 3 clock cycles, the optimum tRAS value would be 7 clock cycles.
But if you start getting memory errors or system crashes, increase the tRAS value one clock cycle at a time until your system becomes stable

5. Row precharge time
Common Options : 2, 3, 4
Quick Review
This BIOS feature sets the number of cycles required for the RAS to accumulate its charge before another row can be activated. If the tRP timing value is too long, it will reduce performance by delaying all row activations. Reducing the precharge time to 2 improves performance by allowing a new row to be activated earlier.
However, the short precharge time of 2 may be insufficient for some memory modules. In such cases, the active row may lose its contents before they can be returned to the memory bank and the row deactivated. This may cause data loss or corruption when the memory controller attempts to read from the active row or write to it.
Therefore, it is recommended that you reduce the SDRAM tRP timing value to 2 for better performance but increase it to 3 or 4 if you experience system stability issues after reducing the precharge time.

6. Row cycle time
Common Options : 7, 8, 9, 10, 11, 12, 13
Quick Review
This BIOS feature controls the memory module's Row Cycle Time or tRC. The row cycle time determines the minimum number of clock cycles a memory row takes to complete a full cycle, from row activation up to the precharging of the active row.
Formula-wise, the row cycle time (tRC) = minimum row active time (tRAS) + row precharge time (tRP). Therefore, it is important to find out what the tRAS and tRP parameters are before setting the row cycle time.

If the row cycle time is too long, it can reduce performance by unnecessarily delaying the activation of a new row after a completed cycle. Reducing the row cycle time allows a new cycle to begin earlier.
However, if the row cycle time is too short, a new cycle may be initiated before the active row is sufficiently precharged. When this happens, there may be data loss or corruption.
For optimal performance, use the lowest value you can, according to the tRC = tRAS + tRP formula. For example, if your memory module's tRAS is 7 clock cycles and its tRP is 4 clock cycles, then the row cycle time or tRC should be 11 clock cycles.

7.row refresh cyc time?

8. Row to Row delay
Common Options : 2 cycles, 3 cycles
Quick Review
This BIOS feature specifies the minimum amount of time between successive ACTIVATE commands to the same DDR device. The shorter the delay, the faster the next bank can be activated for read or write operations. However, because row activation requires a lot of current, using a short delay may cause excessive current surges.
For desktop PCs, a delay of 2 cycles is recommended as current surges aren't really important. The performance benefit of using the shorter 2 cycles delay is of far greater interest. The shorter delay means every back-to-back bank activation will take one clock cycle less to perform. This improves the DDR device's read and write performance.
Switch to 3 cycles only when there are stability problems with the 2 cycles setting.

9. Write Recovery Time
Common Options : 1 Cycle, 2 Cycles, 3 Cycles
Quick Review
This BIOS feature controls the Write Recovery Time (tWR) of the memory modules.
It specifies the amount of delay (in clock cycles) that must elapse after the completion of a valid write operation, before an active bank can be precharged. This delay is required to guarantee that data in the write buffers can be written to the memory cells before precharge occurs.
The shorter the delay, the earlier the bank can be precharged for another read/write operation. This improves performance but runs the risk of corrupting data written to the memory cells.
It is recommended that you select 2 Cycles if you are using DDR200 or DDR266 memory modules and 3 Cycles if you are using DDR333 or DDR 400 memory modules. You can try using a shorter delay for better memory performance but if you face stability issues, revert to the specified delay to correct the problem.

10. Write to Read Delay
Common Options : 1 Cycle, 2 Cycles
Quick Review
This BIOS feature controls the Write Data In to Read Command Delay (tWTR) memory timing. This constitutes the minimum number of clock cycles that must occur between the last valid write operation and the next read command to the same internal bank of the DDR device.
The 1 Cycle option naturally offers faster switching from writes to reads and consequently better read performance.
The 2 Cycles option reduces read performance but it will improve stability, especially at higher clock speeds. It may also allow the memory chips to run at a higher speed. In other words, increasing this delay may allow you to overclock the memory module higher than is normally possible.
It is recommended that you select the 1 Cycle option for better memory read performance if you are using DDR266 or DDR333 memory modules. You can also try using the 1 Cycle option with DDR400 memory modules. But if you face stability issues, revert to the default setting of 2 Cycles.

11. Read to Write Delay
Common Options : 1 Cycle, 2 Cycles
Quick Review
This BIOS feature controls the Write Data In to Read Command Delay (tWTR) memory timing. This constitutes the minimum number of clock cycles that must occur between the last valid write operation and the next read command to the same internal bank of the DDR device.
The 1 Cycle option naturally offers faster switching from writes to reads and consequently better read performance.
The 2 Cycles option reduces read performance but it will improve stability, especially at higher clock speeds. It may also allow the memory chips to run at a higher speed. In other words, increasing this delay may allow you to overclock the memory module higher than is normally possible.
It is recommended that you select the 1 Cycle option for better memory read performance if you are using DDR266 or DDR333 memory modules. You can also try using the 1 Cycle option with DDR400 memory modules. But if you face stability issues, revert to the default setting of 2 Cycles.

12. Refresh Period
Common Options : 7.8 µsec, 15.6 µsec, 31.2 µsec, 64 µsec, 128 µsec, Auto
Quick Review
This BIOS feature allows you to set the refresh interval of the memory chips. There are three different settings as well as an Auto option. If the Auto option is selected, the BIOS will query the memory modules' SPD chips and use the lowest setting found for maximum compatibility.
For better performance, you should consider increasing the Refresh Mode Select from the default values (15.6 µsec for 128Mbit or smaller memory chips and 7.8 µsec for 256Mbit or larger memory chips) up to 128 µsec. Please note that if you increase the Refresh Mode Select too much, the memory cells may lose their contents.
Therefore, you should start with small increases in the Refresh Mode Select and test your system after each hike before increasing it further. If you face stability problems upon increasing the refresh interval, reduce the refresh interval step by step until the system is stable.
10-06-2004, 08:09 AM
ugp

Where did you find that?
10-06-2004, 08:12 AM
Ubermann

Will try find info on all setting and finish it later.
And yes ugp i gonna see what max i can get stock setting 200x10 in a while =)
10-06-2004, 08:15 AM
ugp

Oh sweet thanks man. Yeah I have given up for the time being...need a break from it.
10-06-2004, 08:17 AM
Ubermann

Quote:

Originally Posted by ugp

Oh sweet thanks man. Yeah I have given up for the time being...need a break from it.

Might be your -CO cpu that holds you back, but im still noob so its a guess.
10-06-2004, 08:29 AM
ugp

I have thought that was well too.

I can't seem to get any higher than 3020MB/s

But I am also testing this with 2 DIMMs

EDIT: I take that back I jsut got 3027MB/s.

FSB BUS Frequency: 200
AGP BUS Frequency: 66
Clock Spred Spectrum:
LDT Downstream Width: AUTO
LDT Upstream Width: AUTO
LDT/FSB Frequency Ratio: AUTO
CPU/FSB Frequency Ratio: 10.0
CPU VID Control: 1.550V
CPU VID Special Control: AUTO
ChipSet Voltage Control: 1.6V
AGP Voltage Control: 1.5V
DRAM Voltage COntrol: 2.8V

DRAM Frequency Set (MHz): 200MHz 1:1
Command Per Clock (CPC): 1T
CAS Latency Control (TCL): 2
RAS# To CAS# Delay (TRCD): 2
Min RAS# Active Time (TRAS): 5
Row Precharge Time (TRP): 2
Row Cycle Time (TRC): 12
Row Refresh Cycle Time (TRFC): 14
Row To Row Delay (TRRD): 2
Write Recovery Time (TWR): 3
Write to Read Delay (TWTR): 1
Read To Write Delay (TWTR): 1
Refresh Period (TREF): 200MHz 3.9us
Write To CAS Latency (TWCL): AUTO

DQS Skew Control: AUTO
DQS Skew Value: AUTO
DRAM Drive Strength: AUTO
Max Async Latency: 7
Read Preamble Time: 5
Idle Cycle Limit: 16
Dynamic Counter: ENABLED
R/W Queue Bypass: 8x
Bypass Max: 4x
32 Byte Granularity: AUTO

That is what I used...Alot of it was set to AUTO but I pulled up A64 Tweaker and got the settings it assigned.

And also it was a 43s SuperPi time.

Even at stock speeds I still scored 7144 on 3DMark03. Not bad if you ask me :D
10-06-2004, 09:02 AM
pokipoki

I would like to understand OCZ Platinum Rev. 2's timings and FSB range, perhaps someone have tried and can comment.

Q1 : What is the lowest timings these DDR can do at FSB 233 & 250MHz 1:1 DC on i865PE/i875P? Does the chipset bootstrap (133/166/200MHz) play a part?

or

Q2 : Is it possible to attain 2-2-2 or 2-3-3 on i875P at 1:1 DC FSB 233/250MHz on chipset bootstrap 133/166MHz? I know it's a messy situation, I apologise... Any comments appreciated.

Thank you.

Regards,
pokipoki
10-06-2004, 09:10 AM
Ubermann

I get 3144 in sandra at 200x10
ugp choose 166 instead of 200mhz at "Refresh Period (TREF): 200MHz 3.9us"
And you gain almost 100meg in sandra.

Poki dunno if someone here run them with intel.
10-06-2004, 09:38 AM
Nimrod0031

Very nice post about settings ubermann
10-06-2004, 09:41 AM
Ubermann

Will ask jess if i can use hes recommended settings for bios in that "guide"
10-06-2004, 09:52 AM
ugp

I want to know the optimal settings for best performance/bandwidth that the EL Plat Rev 2 will handle.
10-06-2004, 10:26 AM
pokipoki

Quote:

Originally Posted by Ubermann

I get 3144 in sandra at 200x10
ugp choose 166 instead of 200mhz at "Refresh Period (TREF): 200MHz 3.9us"
And you gain almost 100meg in sandra.

Poki dunno if someone here run them with intel.

Thanks for the reply. So, bootstrap does play a part even for AMD or is it just Sandra? I asked at OCZ forums about i875P performance a few days ago, maybe they missed it.

Sorry, I'm not familliar with AMD platform, but is strap 166MHz officially supported? Could Sandra mislead results on an unsupported bootstrap?

Regards,
pokipoki
10-06-2004, 10:48 AM
Ubermann

Poki i really dont know anything about intel.
Im new to overclocking and dont even know what bootstrap is.
Can you explain what it is ?
If you mean Refresh Period (TREF) then you can choose from 100 to 200mhz on this board with different value on each.

Im trying to learn A64 and this ram.

Google and logic is your friend =)
10-06-2004, 10:52 AM
Ubermann

What is your max fsb with 2 sticks ?
I can do some benches at that fsb and mess with timings and bios to try find some optimal setting.
But not sure if that result would be same with 2 sticks.

Quote:

Originally Posted by ugp

I want to know the optimal settings for best performance/bandwidth that the EL Plat Rev 2 will handle.
10-06-2004, 10:53 AM
ugp

Quote:

Originally Posted by Ubermann

I get 3144 in sandra at 200x10
ugp choose 166 instead of 200mhz at "Refresh Period (TREF): 200MHz 3.9us"
And you gain almost 100meg in sandra.

Poki dunno if someone here run them with intel.

Which 166? There are a few different ones to choose from..
10-06-2004, 10:55 AM
Ubermann

Try the 166 7.8us
10-06-2004, 10:55 AM
ugp

Quote:

Originally Posted by Ubermann

What is your max fsb with 2 sticks ?
I can do some benches at that fsb and mess with timings and bios to try find some optimal setting.
But not sure if that result would be same with 2 sticks.

I am having trouble finding my max overclock without any errors in MemTest-86 :( This is why this sucks so bad. I can hit 290 one 1 stick and 280 on another stick without errors in MemTest-86 but I get memory dump errors in windows before it even finishes loading to my desktop. I do not understand it at all.
10-06-2004, 10:56 AM
ugp

Alright I'll give it a shot after this DVD finishes burning...

Quote:

Originally Posted by Ubermann

Try the 166 7.8us
10-06-2004, 11:01 AM
Ubermann

You run XP SP1 ?
What chipset volt ?
10-06-2004, 11:08 AM
ugp

Quote:

Originally Posted by Ubermann

You run XP SP1 ?
What chipset volt ?

I am running SP2 and I am using v1.6

What is the best TRC & TRFC?
10-06-2004, 11:10 AM
Ubermann

Use Chipset 1.8 (put a fan blowing on it, i never seen it go over 50c with 1.9v) and throw SP2 in the garbage.
I cant even boot win with my settings and SP2.
10-06-2004, 11:16 AM
pokipoki

Quote:

Originally Posted by Ubermann

Poki i really dont know anything about intel.
Im new to overclocking and dont even know what bootstrap is.
Can you explain what it is ?
If you mean Refresh Period (TREF) then you can choose from 100 to 200mhz on this board with different value on each.

Im trying to learn A64 and this ram.

Google and logic is your friend =)

Thanks for the reply. Short question, on AMD - what's the highest FSB you can run on 2-2-2-5? and 2-x-x-x? Thanks again

regards,
pokipoki
10-06-2004, 11:19 AM
Ubermann

A cas on 2 wont bring it higher the 220fsb i think.
Never tried 2-3-3 and such, will do it now.
10-06-2004, 11:20 AM
Zeus

Raising chipset voltage did bugger all for me.
I could boot at 420HTT with just 1,6V on the chipset, 1,7 or higher didn't make any difference.

Uber,
Did you try all dimm slots individual?
For me slot 1 appeared to be worse than 2 and 3.

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