8GB OCZ On The LP UT X48-T3RS DDR3 Board. Post 1 Of 2
DFI LP UT X48-T3RS, 06/09 BIOS
E8400
480x8.5, Memory 1600MHz
2x2GB OCZ PC3-12800 1600MHz Platinum EB
2x2GB PCZ PC3-10666 1333MHz ReaperX
XFX8800 GTS (G92)
tRD - 8.3, Memset Misreads The Value When Set Manually
Memory Speed - 1600MHZ, CPU-Z Misreports The Divider
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http://www.edgeofstability.com/image...ios/main_s.jpg http://www.edgeofstability.com/image...ios/volt_s.jpg
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http://www.edgeofstability.com/image...s/dram_1_s.jpg http://www.edgeofstability.com/image...s/dram_2_s.jpg
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http://www.edgeofstability.com/image.../clock_1_s.jpg http://www.edgeofstability.com/image.../clock_2_s.jpg
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http://www.edgeofstability.com/image...os/phase_s.jpg http://www.edgeofstability.com/image.../feature_s.jpg
Code:
CPU Feature Page
Thermal Management Control................Enabled
PPM (EIST) Mode...........................Disabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Disabled
Virtualization Technology.................Disabled
Core Multi-Processing.....................Enabled
Main BIOS Page
Exist Setup Shutdown......................Mode 2
Shutdown After AC Loss....................Disabled
O. C. Fail Retry Counter..................0
CLOCK VC0 Divider.........................Auto
CPU Clock Ratio...........................8.5x
CPU N/2 Ratio.............................Enabled
CPU Clock.................................480 MHz
Boot Up Clock.............................Auto
CPU Clock Amplitude.......................800mV
CPU Clock0 Skew...........................0ps
CPU Clock0 Skew...........................0ps
DRAM Speed................................400/1333
PCIE Clock................................100MHz
PCIE Slot Config..........................1X 1X
CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled
SATA Spread Spectrum......................Disabled
Voltage Setting Page
CPU VID Control...........................1.36250V
CPU VID Special Add Limit.................Enabled
CPU VID Special Add.......................Auto
DRAM Voltage Control......................1.874V
SB Core/CPU PLL Voltage...................1.510V
NB Core Voltage...........................1.630V
CPU VTT Voltage...........................1.200V
VCore Droop Control.......................Disabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Weak
GTL REF Voltage Control...................Disabled
CPU GTL 1/2 REF Volt......................113
CPU GTL 0/3 REF Volt......................100
North Bridge GTL REF Volt ................100
DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Disabled
Clock Setting Fine Delay..................Listed Below
CAS Latency Time (tCL)....................7
RAS# to CAS# Delay (tRCD).................6
RAS# Precharge (tRP)......................6
Precharge Delay (tRAS)....................20
All Precharge to Act......................7
REF to ACT Delay (tRFC)...................60
Performance Level.........................9
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................18
Rank Write to Read (tWTR).................13
ACT to ACT Delay (tRRD)...................4
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............Auto
Ranks Read to Read (tRDRD)................Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................5
ALL PRE to Refresh........................7
Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Enabled
Channel 1 Phase 1 Pull-In.................Enabled
Channel 1 Phase 2 Pull-In.................Enabled
Channel 1 Phase 3 Pull-In.................Enabled
Channel 1 Phase 4 Pull-In.................Enabled
Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Enabled
Channel 2 Phase 4 Pull-In.................Enabled
Clock Setting Fine Delay Page
DRAM Default Skew Model...................Model 3
Fine Delay Step Degree....................50ps
Ch1 Clock Crossing Setting................Auto
DIMM 1 Clock fine delay...................Current 489ps
DIMM 2 Clock fine delay...................Current 489ps
DIMM 1 Control fine delay.................Current 434ps
DIMM 2 Control fine delay.................Current 473ps
Ch 1 Command fine delay...................Current 550ps
Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current 686ps
DIMM 4 Clock fine delay...................Current 686ps
DIMM 3 Control fine delay.................Current 607ps
DIMM 4 Control fine delay.................Current 654ps
Ch 2 Command fine delay...................Current 700ps
Ch1Ch2 CommonClock Setting................Auto
Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto
Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto
Common CMD to CS Timing...................2N
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http://www.edgeofstability.com/image...8_memset_s.jpg
8GB OCZ On The LP UT X48-T3RS DDR3 Board. Post 2 Of 2
