just ordered a pair of these and should be here wednesday for my asus maximus 2 ... hopefully they actually work ... had some gskill which my board absolutely hated :/
Printable View
just ordered a pair of these and should be here wednesday for my asus maximus 2 ... hopefully they actually work ... had some gskill which my board absolutely hated :/
wow, thanks for the heads-up. Which gskill do u have. I have the same motherboard and it runs really well with my 2x1 GB Ballistix ( 470, ddr1175 ) but I need 4GBs.
Was thinking 'bout the gskill pc8800 but now I have second thought.
mine was the gskill 8500 2x2GB
...my dominators will be here tomorrow and i can post back on how they hold up with this board
Quote:
Originally Posted by Copenhagen69
I had the exact same problems with the G.Skill F2-8000CL5D-4GBPQ on my Asus p5b board and a good friend of mine had the same problems with it on a gigabyte board. The memmory just doesn't work at stock 1000mhz, neither does it overclock very well.. When i insert my "Geil GX22GB64000PDC" i get way better results.
I'm considering of purchasing some of the corsair rams myself.
I just took stock of a Maximus Formula that I promptly flashed into a Rampage, and my Ballistix 8500 kit passed memtest at DDR2-1200 with VDIMM set to 2.2V in the BIOS. Are these newer chipsets just better at running D9 at higher clocks with less voltage, or do they just overvolt by a LOT?
i cant get my pair stable passed 1066.... even 1070 is unstable and cant pass any tests.... guess i got a lame set?
You said your board hated G.Skill, & now you're having issues with Corsair.Quote:
Originally Posted by Copenhagen69
Sounds like something's not set right in the bios man.
And the not so fun thing is, you might need to start digging around in subtimings to get things stable.
tRFC loose? (55+)
tRD loose?
I'd go & loosen every single subtiming a few notches...not joking either.
My P5Q is extremely sensitive to subtimings.
One decrease on the wrong one = unstable.
I actually cannot run auto subtimings as it's not stable. (though this is likely due to 8 GB & being OCed)
Just something to think about...i doubt you got two different RAM kits that are bad.
alrighty n7 ill take a gander at all those and see what i can come up with ... thanks
mine are very happy at 1140 with 2.1 (2.09 shown actual) at 5-5-5-15-52 pl 8 they im sure could do more either maybe tighter timings or same timings and pushed a bit more they are running fine
Hi, would like to join the discussion
Just got my sticks. at first they would not boot at 1066mhz
i had to do 8x444 giving me the following result
http://img116.imageshack.us/img116/9...mhz1210mq9.png
By neo_rtr at 2008-08-04
I would like to do 9x400 1066mhz but the pc will not boot.
Iam thinking of doing some lower speeds with low timings instead.
I have updated to BIOS 12.07 This time i can boot 8x450 1080mhz 5 5 5 15
(was not able to do it before)
http://img181.imageshack.us/img181/8818/prime95vz5.jpg
By neo_rtr at 2008-08-08
sample
http://img113.imageshack.us/img113/1...5151210eh0.png
By neo_rtr at 2008-08-08
The PLL is set to 1.56V this comes up as 1.712V reported by BIOS
I have try it 3 times (SET in Bios 1.66v, 160V & 1.56V) and appears that my system is stable in Prime (so far)
With out PLL set manually the PRIME95 (p95v256 64bit ver.). would fail with in a minute.
With PLL set so far 3 times run the series of tests with out failure.
Nice stuff Neo
I've found my stable 24/7 Orthos blend and Memtest86 stable settings for these sticks at 1147 MHz
This is with the Rampage Formula bios 0308 on my Maximus Formula.
Only 4GB as I sold the other two sticks.
http://img.photobucket.com/albums/v3...gtRD743GHz.png
zlojack: What bios settings are you using that enable you to get 10k+ and that 1147mhz memory?
I'm able to run 1120mhz with my OCZ reaper pc8500, and quite possibly higher because I have not tested for stability above this speed. I think the Dominators were at one time using the same chips as the OCZ reapers, but I'm not sure now.
I do believe that the memory is very similar at least.
BTW: what tRD are you using in that Everest benchmark? I can't seem to get tRD = 6 to work well at all, and tRD = 7 seems to top out at 460fsb...
I've only been playing with this memory/board for a few days though so hopefully I'll figure it out
I use tRD7 with the Rampage Formula bios 0308 flashed on my Maximus Formula. RAM is set at 2.02 in bios which gives 2.1 v actual.
I'll get you the settings later when I have a chance to write them down.
there are a few subtimings which can help a lot when you hit an error wall. tRTPD, tPTP, tRRD, tWTPD, tAPTRD, tAPTAD.
tRTPD (read to pre delay) add min +2 above value of tRP on 2gb sticks.
{
tAPTRD (all pre to ref delay) use tRTP + 2 (read to precharge)
tAPTAD (all pre to act delay) use tRTP + 2 (read to precharge)
} this is because you need to issue the command to all banks on same rank, you allow an extra clock to make sure they all receive the command, which is where the 2 comes from.
tRRD (act to act delay) basically you need to allow a slightly longer delay to ensure that when issuing a consecutive activate command that you allow at least enough time that the first activate command has arrived before activating another bank on the same rank, reason being that with four ranks you have double the amount of banks on each dimm and the chance of collisions on the bus becomes alot greater in a row cycle.
tWTPD (write to pre delay) little more time to complete write strobes usually results in lower latency and less errors / slowdowns, 14 - 16 are fine.
tPTP (pre to pre delay same rank) default is 1, which is ridiculously tight and i've seen it cause random errors at higher dram frequencies on certain IC's. 3 is the highest you can set, 2 is a good value for cautiousness. I havent in my experience found a value of 3 to be beneficial or help with errors at that point.
tRFC (refresh cycle turnaround) max turnaround between any two refresh commands. 8 bank / 4 rank sticks need at least 1.7x the amount of clocks for turnaround than the equivalent 4 bank / 2 rank sticks. Check JEDEC specs for DDR2-1066 and you will understand further. 1066 requires a minimum of 105ns for tRFC with 8 bank/4 rank due to FBAW (four bank active window) command turnaround (minimum time it takes for four banks active on any rank to complete their cycle which adds quite a large clock latency to ensure that any further activates dont collide or queue up and slow down bus traffic. 2 bank / 4 rank (256x4) 1gb sticks dont use FBAW so they can complete a refresh cycle alot more quickly, minimum for them is 54 or 56ns.
At 1066mhz CL5, tCK (clock period) is 533 / 5 (data freq / cas latency), 1.86ns. So to get tRFC from 105ns at 1066mhz, you would do 105 / 1.86, which gives you a timing value ~ 60t or so. Sometimes loosening tRFC up improves performance, as a more consistent queue of data from ram to cpu even though its slower to arrive still leave less unused clocks wasted rather than intermittent bursts then traffic jams and so on.,
other timings dont seem to have as large an influence as these do.
skews can have a large influence, and they are only relevant to a given frequency. they do change as you get farther from the previously skewed target frequency. you need to figure out how your particular board responds to skew changes and when it likes/dislikes them. it's a lot of trial and error, and guesswork. sometimes you can pick out which way skews need to be, but its not always obvious unless you are using really high dram frequency and fsb.
^Good info, which I have also found to be correct from my testing. D9 IC's allow you to have relatively very tight primary and secondary timings, however a lot of the newer IC's require a lot of trial and error to figure out what they need to be stable at a given frequency.
Here are my settings bios 0308:Quote:
Originally Posted by Archmage
mikeyakame...any suggestions for tightening there or for squeezing out more bandwidth?Quote:
Ai Overclock Tuner : Manual
OC From CPU Level Up : AUTO
CPU Ratio Control : Manual
- Ratio CMOS Setting : 9
FSB Frequency : 478
FSB Strap to North Bridge : 333
PCI-E Frequency: 100
DRAM Frequency: DDR2-1148
DRAM Command Rate : 2N
DRAM CLK Skew on Channel A: Normal
DRAM CLK Skew on Channel B: Normal
DRAM Timing Control: Manual
CAS# Latency : 5
RAS# to CAS# Delay : 5
RAS# Precharge : 5
RAS# ActivateTime : 15
RAS# to RAS# Delay : 3
Row Refresh Cycle Time : 60
Write Recovery Time : 6
Read to Precharge Time : 3
Read to Write Delay (S/D) : 8
Write to Read Delay (S) : 3
Write to Read Delay (D) : 5
Read to Read Delay (S) : 4
Read to Read Delay (D) : 6
Write to Write Delay (S) : 4
Write to Write Delay (D) : 6
Write to PRE Delay : 14
Read to PRE Delay : 5
PRE to PRE Delay : 1
ALL PRE to ACT Delay : 6 (5 here gave me higher latency)
ALL PRE to REF Delay : 6 (5 here gave me higher latency)
DRAM Static Read Control: Enabled
Ai Clock Twister : Strong
Transaction Booster : Manual
Common Performance Level [7]
Pull-In of CHA PH1 Disabled
Pull-In of CHA PH2 Disabled
Pull-In of CHA PH3 Disabled
Pull-In of CHA PH4 Disabled
Pull-In of CHA PH5 Disabled
Pull-In of CHB PH1 Disabled
Pull-In of CHB PH2 Disabled
Pull-In of CHB PH3 Disabled
Pull-In of CHB PH4 Disabled
Pull-In of CHB PH5 Disabled
CPU Voltage : 1.41875
CPU PLL Voltage : 1.52
North Bridge Voltage : 1.55
DRAM Voltage : 2.04 (I think it's at 2.12 actual)
FSB Termination Voltage : 1.24
South Bridge Voltage : 1.050
Loadline Calibration : Enabled
CPU GTL Reference : 0.67X
North Bridge GTL Reference : 0.67X
DDR2 Channel A REF Voltage : DDR2-REFF
DDR2 Channel B REF Voltage : DDR2-REFF
DDR2 Controller REF Voltage : DDR2-REFF
SB 1.5V Voltage : 1.5
I realize I'll have to try and test myself, but suggestions are welcome. :D
MCH tRD Phase Pull-ins are your best friend. If you can't tighten down to PL6, try pull in CHA PH1 , CHB PH1, CHA PH 4, CHB PH4, CHA PH5, CHB PH5 and see if passes Memtest86+ first or even posts. Pull in one at a time, and test each time. Pulling in individual phases carelessly when the lower PL is unpostable can cause cmos corruption, so if you choose to play with these keep a copy of your current bios settings in one of the OC profiles in case. I've corrupted my cmos data many a time when doing this, but It was the only way to understand the effect each has and what to not do! Always Pull in PH1 first, since this phase effects clock signal phase between DRAM and MCH, then depending on divider you are using the next ones will not always be the same. You're using to 5:6 which can be seen by number of phases for each channel.
1:1 has 2 phases / channel which is the bare minimum. (clock phase and data phase)
The other dividers which have more than 2 phases still have the same clock and data phase pull ins, but there are more of each.
3:4 has 3 phases /channel, 2 clock phase (PH1, PH2) and 1 data phase (PH3)
4:5 has 4 phases / channel, 3 clock phases (PH1-3) and 1 data phase (PH4)
5:6 has 5 phases / channel, 4 clock phases (PH1-4) and 1 data phase (PH5)
You just need to be careful when choosing Phases to pull in , you need to be able to comprehend the difference when divider changes if you do. Rule of thumb is if you can't pull in Phase 1 of CHA or CHB then you will not pull in any others. More NB voltage can help sometimes but depending on your FSB clock freq, DRAM clock freq, NB cooling, memory timings and even memory IC's you won't go any farther. You generally need less NB voltage to pull in a few phases to the lower Peformance Level, than to completely change all phases to lower PL. How much varies, and its scales as you go lower. Whatever you needed extra to get the current Performance level, will require generally at least 2 times the previous jump in voltage to go one lower. I know on my Ramapge to even Pull in certain phases to PL5 from PL6 I needed to add 0.1V, 1.53 -> 1.63V. PL7 -> PL6 at 440FSB needed 0.14V (1.39V -> 1.53V). PL6->PL5 at that frequency needs at least 0.25V more to post, I stopped trying after I got to 1.67v NB as even if you can supply enough voltage the NB has to run at high 30s/low 40s to be stable with PL5, so generally under water. PL6 stability is usually below high 40s.
You will gain decent amounts if you have some more fine adjustment in the tRD pull-ins and it's error free. In both memory latency and read speeds.
In my personal experience I found 5:6 to be the best divider to use on the Rampage, probably due to not having enough phases on the VRM. More VRM phases generally helps higher dividers to be more stable at high FSB. The Rampage Extreme with dual 8 phase VRM is alot more stable with higher FSBs and higher dividers. The Formula has a sucky 1:1 divider thats for certain. I tend to use 4:5 or 5:6, which are 400 and 333Mhz FSB straps respectively. The others refuse to post or can't be made stable enough above 450FSB with a quad core. I haven't tried a dual core on this board, so your experience maybe a little different to mine in regards to which divider/s you can and can't use beyond 450FSB. Only divider I could get 500FSB to post on with my quad core was 5:6, the others all refused to post period. 5:6 took a lot of fine adjustment to get to post at 500FSB, but I couldn't get my ram to be stable at 1200MHz which was a little disappointing!
Thanks zlojack and mike!
That was some excellent information :yepp:
I'll put it to good use.
Thanks mikeyakame, that's some very good information there. I learn something on these forums almost every day!
I'll play with that stuff tonight! I find the 5:6 divider works well for me (333 strap) while I haven't really tried the 4:5. I'm not sure if this RAM can get up to 1195 MHz stable, but it will be fun to try. PL6 doesn't post for me.
http://img87.imageshack.us/img87/962...bsrrt45xg7.png
By neo_rtr at 2008-08-14
Iam running 8x455 ddr2 1092 5-5-5-12 , 3 45 6 4subtimes
Dream Static Read Control Auto
Ai Clock Twister. Strong
Transaction boster Disable
Glad to be of help!Quote:
Originally Posted by zlojack
The Rampage can be really temperamental at high FSB and takes a lot of trial and error to get it to work right, but with patience you can prevail. Sometimes it takes no trial at all and works, then change a setting or 3 and it refuses to post!
The easiest way I figured out to test memory timings is to boot Memtest86+, go to the configuration menu, select #5 test and then continue back. Moving blocks around memory is extremely strenuous and will almost always bring out any timing errors.
If it successfully does 5 passes of #5 for me then I'll reboot and let it run a full test pass. It will almost always pass if you can get through 4 or 5 passes of #5. This way any problems that are left are usually easy to isolate with Prime95, OCCT or the likes, and I've found are generally due to CPU/NB GTL REF, vNB or vCore.
You can also easily spot if PLL needs adjustment by just watching how graphics are drawn on screen. if the image is rendered in out of order pixel areas then you probably have a PLL voltage which is either too high or low, this one is a bit of guess work and mostly noticing inconsistencies.
Nice.
Well, I've been able to pull in Phase 1 of Channel A and it passes 6 hours of Memtest86+, but if I try to pull in Phase 1, Channel B, I get no post with DETDRAM error.
I've bought these babbis as well. Plays well with my motherboard.
Subscribed for further info.
I'm picking up a kit of these on Monady, can't wait!
I plan on running them at 533MHz FSB 1:1 just to start with :D