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yeah what he says.Quote:
Originally Posted by alexio
Just think about it, and how HT works.
With Conroe monster 4 decoders, short pipeline, and micro ops fusion, there are hardly any pipeline bubbles at all for HT to take advantage of. I bet you if somehow Intel introduced conroe chips with HT, it would actually be slower in majority of benchamrks.
Actually, it seems that the Core architecture would be a superior system to deploy HyperThreading on compared to the P4.
It seems to be a common misconception that the purpose of HyperThreading is to deal with pipeline stalls. This is not entirely accurate (though it helps, I guess) The real purpose of hyperthreading is to maximize the use of the processor's parallel instruction execution. Afterall, in the P4, it's a 3 issue core that can theoretically do 3 instructions in parallel in one cycle. However, it is very very rare that a single thread is capable of using all 3 execution units at once.
Hyperthreading allows multiple threads to mix together in a single clock cycle to try to maximize the use of the execution units in parallel. This is a rather poor explanation (and wrong on so many levels) but I think it makes the most sense. In a traditional CPU, let's say the processor manages to use OOE to run two operations at once. Let's say it uses the integer execution unit and FPU execution unit (a gross oversimplification, but go with it.) However, let's say the processor has another integer execution unit. It has to go idle, because the processor couldn't find anything to fill it with.
With hyperthreading, however, it is possible for the CPU to take another thread and say "Well, hrm, this has an integer operation I could sneak in with.. let's run this in parallel with the other thread to fill all three of my execution units! Sweet!" This actually increases the efficiency of the processor, because it's doing more work in a single cycle. This is how a processor can magically do a bit more work with HT enabled in many cases. In regular processing, CPU's are extremely wasteful. Even with the most advanced OOE algorithms, most of the time much of the CPU's execution units go unused.
The Core architecture would be able to take advantage of the 4-issue core (technically 5 issue if you include micro/macro-ops fusion) with HT much moreso than the Pentium 4's 3-issue core. Once again, this is a gross oversimplification, but you get the general idea.
I would assume there are numerous reasons why Intel did not include HT in the new architecture. First and foremost, I think that they figured that for everything besides servers, dual cores are enough to deal with all of the threads that an average CPU would run. Afterall, how often do you max out both cores? The only thing I can think of is things like rendering and encoding, which is something that the average user simply doesn't do. Even in multi-threaded games, there is usually a heavy bias on one core or the other and there is still plenty of idle time on the extra core. In short, it was better to use the transistor space for other things to increase single-threaded performance. The second reason has already been mentioned. Perhaps the advanced micro/macro-ops fusion wrecked havok on trying to use HT for whatever reason.
I wouldn't really expect HT to show up on the XE CPU's. I would expect them to show up on Woodcrest CPU's, because that is where you are most likely to gain performance from HT - heavily threaded multi-user environments.
Then again, who knows what Intel is thinking. I'm sure there was a good reason as to why not to include HT. Afterall, HT has been known to slow some things down. Maybe adding HT cluttered up the processor too much - a lot of overhead in different things that added unnecessary complexity. Who knows.
Woodcrest (Xeon 51xx-series chips) will work in all Socket 771 boards, its simply that Dempsey (the Xeon 50xx series chips) has launched with the Bensley platform and Woodcrest is coming later.Quote:
Originally Posted by Schlotkins
All the boards are designed for Woodcrest. :)
That's cool - too bad all of the boards use FB-DIMMs... they are pretty pricey.Quote:
Originally Posted by Thorburn
As you know I disagree. As I already explained, with the fusion, other optimizations etc, all the units are kept pretty busy, so trying to squeeze in another thread to get them as close as possible to 100% busy would:Quote:
Originally Posted by ethernal
1. add lots of extra high power hungry dynamic logic
2. muddle up the caches, and reduce hit rate ratio
3. Introduce overhead of repeated switching due to race conditions, and deadlocks (not sure on this one.. its been a long while since I studied this stuff)
4. add extra demand on resources, especially the few load/store units, already demanding lots of bandwidth, not to mention mess up prefetche.
5. It just doesnt feel right for a short pipeline processor with so little wiggle room, focusing on getting stuff done quickly rather than having hundreds of instructions in flights, spending dozens of clock cycles re-arranging instructions in huge ROB queues.
However, I totally agree with you about the last point. Intel wouldn't have gambled billions of dollars and many years of research and development if they didn't know what they were doing.
Cool and I hope that mess with is Fugger is cleaned up. He's one of my Favorite folks here and not because of his statis. I think it had something to do with that Dare tag line in his sig he had that went like; If you think you rig is faster than mine, prove it, LOL!Quote:
Originally Posted by FLG_Poncho
Well done Fugger . This was started befor things were changed by intel .Quote:
Originally Posted by FUGGER
Most of us were exspecting The 3.33ghz. 1333 FSB Conroe Intel has backed that off to another date. Poncho since you have a 2.93XE Conroe can you say if the multipliers are unlocked up. If they are not what does the XE model offer to the O/C community.. Since you won't show us any Bench runs . Hows about a CPU-z shot .Here is part of your post at [H] I can't help but noticing that when you posted SS of CPU-z you said that it wasn't giving the correct info because its normal on an ES cpu. DO you have an ES cpu or is it XE? You seem to be saying its an ES cpu in the SS. So if you have an 2.93ghz ES =XE what does it offer that makes it worth $1100+ . Isn't intel releasing a normal Conroe CPU @ 2.93GHz. Can you give us any info backed up with a SS that makes XE more valueable than a normal Conroe????
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05-14-2006, 05:44 PM #1
Poncho Limp Gawd
Baby's first Conroe...
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Well... finally got the goods and updated the old box... Specs at the bottom
Old system:
Intel D975XBX Rev 302 (re-worked, Conroe WILL NOT run on unmodified Rev 302 975 board)
Video Cards... Old and Busted (850XT Platinum) and the New Hottness (X1900XTX):
Installed on tray:
Tray with video card and sound card:
In the chassis:
Outside shot (got rid of the LCD. Never used it anyway, was just to do it)
CPU-Z Shots (The Proc is reading a bit funky there, though it's typical with ES chips)
The X6800 is unlocked up and down.
I was under the impression that in a processor like the p4 or athlon the decoders decode a maximum of 3 CISC aka x86 instructions. All modern CPUs are RISC, whose instructions contain only a single operation, while CISC which all code is written in contains 2-4 like load, add, and store in a single instruction. Assuming 3 x86 instructions are decoded to 6-10 RISC micro-ops, you could take up all execution units on the Athlon, P4, or pentium m. This would also include the load & store.Quote:
Originally Posted by ethernal
Read this by Johan De Gelas from Anandtech...
"A first for the x86 world, the Core architecture is equipped with four x86 decoders, 3 simple decoders and 1 complex decoder. The task of the decoders - for all current x86 CPUs - is not only to decipher the incoming instruction (opcode, addresses), but also to translate the 1 to 15 byte variable length x86 instructions into - easier to schedule and execute - fixed length RISC-like instructions (called micro-ops).
The most common x86 instructions are translated into a single micro-op by the 3 simple decoders. The complex decoder is responsible for the instructions that produce up to 4 micro-ops "(just one decoder, and athlons have 3 complex decoders)". The really long and complex x86 instructions are handled by a microcode sequencer. This way of handling the complex most CISC-y instructions has been adopted by all modern x86 CPU designs, including the P6, Athlon (XP and 64), and Pentium 4."
You can get even more info on Wikipedia by doing RISC and CISC searches.
This would explain why Intel put 2 simple integer units running at 2x the cpu clock on the p4, having a maximum of 4 intructions per clock, above 3. It would make sence for them to only run it at the normal clock rate if 3 intruction were the max, since if would be so unlikely for every instruction to be a simple integer calculation and it would probably increase yields. K8L is going to have twice as many FPU/SSE units and they will be 128bit, quadrupling how many instructions it can do, giving a total of 12 maximum 64bit instructions, and thats just floating point and SIMD, integer units are another 3 and I don't know how many the L&S can do. Isn't that extremely inneficient if there are only 3 operations at the most, why didn't they add any more decoders? Many critics have been skeptical that Conroe's extra decoder will increase performance, and I think this explains why.
Sorry this was a little off topic, but I just wanted to say that.
On topic, there's been hints from Anandtech and the INQ that AMD has something special in store to cempete on the high end, most likely a very high clocked FX, possibly 65nm. AMDs roadmaps have always been terrible so I wouldn't be surprised at all. Maybe this will spur Intel to release a faster CPU. The thing is higher official clocks won't really change what the chip is capable of, so it really will just mean a decrease in price.
Poncho, for an 'insider' you are supremely un-informed.
The X6800 is unlocked.
A program like Crystal CPUID will allow you to change the multiplier in Windows.
http://crystalmark.info/software/Cry...D/index-e.html
Not sure if you want to try it, but there it is.
It should have a higher multiplier than 11 because a Japanese overclocker just set a SuperPi record with an XE and he was using 12.
http://www.xtremesystems.org/forums/...d.php?t=100978
He also happens to work in the enterprise department and probably doesn't care if it's unlocked or not. On [H] he said that he wasn't really into overclocking anyway.Quote:
Originally Posted by Thorburn
not into overclocking......oh my....
Quote:
Originally Posted by FLG_Poncho
i know exactly what your talking about. I tend to overclock in spurts.
some months i push it to its max other months i'll run all stock settings.
Overclocking doesn't have to sacrifice stability. By 1.8Ghz stock X2 165 is as stable as it is at stock speeds and at 3.0Ghz with voltage that's 0.15v over stock. That's one hell of a good deal.Quote:
Originally Posted by FLG_Poncho
There's a board mod that will unlock a number of BIOS features.Quote:
Originally Posted by FLG_Poncho
http://www.xtremesystems.org/forums/...99&postcount=1
Scroll down to the third image.