I tried AMD Auto Clock =>
What it does is, full load your system + 1.33GB RAM, checking it for load instabilities and after a while stable, within 10ms it drops load, empties RAM, increases HT Ref. by 1MHz, thus your overall clocks and ramps load back up. It keeps going until it finds an instability (usually a freeze);
i.e., if it starts at 200x14.5 2900 and it gets past 3011MHz on your clocks, it changes multi to next one up [where possible].
It gave me 204x15 3060MHz full load stable, 205 failed [I'll catch ss next time and post it later] - voltage was 1.460v ID / 1.440v LD, creates very high load
Here's it working half way, going up from 2800/2200
http://img132.imageshack.us/img132/5712/au2rr4.png
But the cold facts are, whilst that much I've already had software load stable many times before, it is still not stable during idle/WISE, hence unstable :(
Quote:
Originally Posted by
d412k5t412
KTE: I actually havn't updated Everest in a while, and I just did. Now its giving me All 4 cores and CPU temp, before it was just CPU. Which one should I go by? CPU or Core? Thanks :)
Both, one diode is a pin diode + offset + BIOS/application offset (same as you see in BIOS usually) and the other is from many Tjunction CPU/IMC diodes as one sensing feedback. Use the "Core" ones to check temps because its linked to the TCC - personally I would advise to stay below 75C full load in it with 9850BE/9750/9100 but the actual Tctl_max limit is 115.5C on these CPUs before throttling or damaging temperature is reached [i.e. Tcase_max]. The register checks confirm what I know from AMD previously too when I complained about how low the Max rated temp was (assuming it was 70C).
Quote:
Originally Posted by
Brother Esau
Whats PTuner? Is that Motherboard Specific Software?
Like SocketMan says ;)
Accurate if you can have it calibrated against known measurements. Voltages tend to be off due to measurement point [source rather than end terminals - so there's a loss (-) to add].
Quote:
Originally Posted by
SocketMan
It's software that comes with Gigabyte GT Power supplies ;)
Speaking of which does the 550w version have the voltage increase slider?(see pic)
Yep, same thing.
Quote:
KTE maybe your WISE instabilities are caused by something other then the CPU, like a video card/ram/ (hopefully not) motherboard (as I just got one) or a combination of the above?
Its not RAM/GPU, since I have X2/Intel systems that I've checked them in. If its MB, I'm not sure. You have the MSI? :shrug:
Quote:
Originally Posted by
Tony
KTE
Initial tests of P0J over 141 show the following.
Boot with Autoxpresss enabled brings on Yellow in AOD
Winrar scores are slightly higher than 141 as long as I set red in AOD
cinebench no different either yellow or red
I will continue to test, as for now I think 141 is the same bios with autoxpress just hidden ( I will recheck with amibcp)
I hit the same clocks, get the same ram speeds and the same bandwidth with both, even in everest.
Remember im using 4GB 2x2 in vista 64 vanilla, 5-5-5-15-11 1000mhz
T
Hmm.. Tony I've no idea what is happening. I'm on P0J, much lower than you in MHz, but here's the scores I have [AOD yellow]
http://img137.imageshack.us/img137/4...2200ie2.th.png http://img210.imageshack.us/img210/6...8432hz3.th.png
My CB10 trend is same as yours and so is WinRAR [with AOD buttons]
Green is no go, low perf.
I'll post 500 5-5-5-15-11 scores after this with 2x1GiB.
Mathos, you can get lower than 0.8v on B2/B3 if you drop clocks enough. We've had 0.4xv pretty easily. 0.8v is lowest rated per the CnQ rated spec, which is 1GHz lowest, if you go below it, which is easily possible, you'll be able to drop below. For K10 lowest and upper CPU/NB voltage boundaries (Serial and Parallel for VRMs) are <very low> to 1.550. See BKDG. Can I ask how you know 0.8-1.4v is the Phenom design limit? :)
Just checked 9850BE capabilities encoded within CPU [look at them carefully ;)]:
MP capability -> F3xE8 [18:16] = 111b = 1 processor max supported
DdrMaxRate -> F3xE8 [7:5] = 100b = 800 MT/s max supported
L3Capable -> F3xE8 [25] = 1b = L3 present
DiodeOffset -> F3xE4 [7:5] = 30h = +11C
MaxNbFid: maximum NB COF -> MSRC001_0071 [63:59] = 00h = unlimited
MinVid: minimum voltage -> MSRC001_0071 [63:59] = 00h = unlimited
MaxVid: maximum voltage -> MSRC001_0071 [41:35] = 00h = unlimited
[current] MemClkFreq -> F2x[1, 0]94 [2:0] = 011b = 400MHz (DDR2-800)
[This field specifies the frequency of the DRAM interface (MEMCLK) - DDR3-1600 is already supported by K10h]
ECX 23:16 L1 data cache associativity = 2
ECX 15:8 L1 data cache lines per tag = 1
EDX 23:16 L1 instruction cache associativity = 2
EDX 15:8 L1 instruction cache lines per tag = 1
EDX 6 100MHzSteps: 100 MHz multiplier Control = 1
EDX 5 STC: software thermal control (STC) is supported
EDX 4 TM: hardware thermal control (HTC) is supported
EDX 3 TTP: THERMTRIP is supported = 1
EDX 2 VID: Voltage ID control is supported = 0 (function replaced by HwPstate).
EDX 1 FID: Frequency ID control is supported = 0 (function replaced by HwPstate).
EDX 0 TS: Temperature sensor = 1.
IddDiv: current divisor field -> MSRC001_0068 Current P-State [41:40] = 01b = IddValue / 10 A
IddValue: current value field -> MSRC001_0068 Current P-State [39:32] = EEh = 238 / 10 A = 23.8A per core
Loadline Vdd = 1.376v
Stock 9850BE: 4*(1.280*23.8) = 122W max power
OC 2800/2200: 4*(1.376*23.8) = 131W max power
HtcPstateLimit: HTC P-state limit select -> F3x64 [30:28] = 001b = P-State 1
[Specifies the P-state limit of all CPU cores when in the HTC-active state]
CurTmp: current temperature -> F3x64 [31:21] = 22h = 34C Tctl
HtcTmpLmt: HTC temperature limit -> F3x64 [22:16] = 01111111b = 127
(F3x64 is not accessible if F3xE8[HTC capable]=0)
9850BE HTCTmpLmt: 52.0 + (0.5 * 127) = 115.5C (Sandra >)
http://img208.imageshack.us/img208/3979/thermalad2.png
HtcHystLmt: HTC hysteresis -> F3x64 [27:24] = 00000010b = 2
[The processor exits the HTC-active state when Tctl is less than HtcTmpLmt minus HtcHystLmt]
9850 exits HTC-active below; 115.5 - 2 = 113.5C
TmpMaxDiffUp: temperature maximum difference up -> F3xA4 [6:5] = 00b = Upward slewing disabled
[if the measured temperature is detected to be greater than Tctl then Tctl is updated to match the measured temperature]
TmpSlewDnEn -> F3x64 [7] = 1h = Slew rate controls in the downward direction are enabled
[0=Downward slewing disabled; if the measured temperature is detected to be less than Tctl then Tctl is updated to match the measured temperature. BIOS should set this bit to 1]
Quote:
2.10 Thermal Functions
Thermal functions HTC, STC and THERMTRIP are intended to maintain processors temperature in a valid
range by:
Providing an input to the external circuitry that controls cooling.
Lowering power consumption by switching to lower-performance P-state or.
Sending processor to the THERMTRIP state to prevent it from damage.
The processor thermal-related circuitry includes (1) the temperature calculation circuit (TCC) for determining
the temperature of the processor and (2) logic that uses the temperature from the TCC. The processor includes
a thermal diode as well.
2.10.1 The Tctl Temperature Scale
Tctl is the processor temperature control value, used by the platform to control cooling systems. Tctl is accessible through SB-TSI and F3xA4[CurTmp]. Tctl is a non-physical temperature on an arbitrary scale measured in degrees. It does not represent an actual physical temperature like die or case temperature. Instead, it specifies the processor temperature relative to the point at which the system must supply the maximum cooling for the processors specified maximum case temperature and maximum thermal power dissipation. It is defined as follows for all parts:
For Tctl = 0 to Tctl_max - 0.125: the temperature of the part is [Tctl_max - Tctl] degrees under the temperature for which maximum cooling is required.
For Tctl = Tctl_max to 255.875: the temperature of the part is [Tctl - Tctl_max] degrees over the worst-case expected temperature under normal conditions. The processor may take corrective actions that affects performance or operation as a result, such as invoking HTC or THERMTRIP_L.
2.10.2 Thermal Diode
The thermal diode is a diode connected to the THERMDA and THERMDC pins used for thermal measurements.
External devices use measurements from the thermal diode measurements to calculate temperature during operation and test. These measurements are required to be adjusted as specified by F3xE4[DiodeOffset].
This diode offset supports temperature sensors using two sourcing currents only. Other sourcing current implementations are not compatible with the diode offset and are not supported. A correction to the offset may be required for temperature sensors using other current sourcing methods. Contact the temperature sensor vendor to determine whether an offset correction is needed.
2.10.3 Temperature-Driven Logic
The temperature calculated by the TCC is used by HTC, STC, THERMTRIP, the PROCHOT signal.
2.10.3.1 PROCHOT_L and Hardware Thermal Control (HTC)
The processor HTC-active state is characterized by (1) the assertion of PROCHOT_L, (2) reduced power consumption, and (3) reduced performance. While in the HTC-active state, the processor reduces power consumption by limiting all CPU cores to a P-state (specified by F3x64[HtcPstateLimit]). See section 2.4.2 [P-states] on page 31. While in the HTC-active state, software should not change F3x64 (except for HtcActSts and HtcEn).
Any change to the previous list of fields when in the HTC-active state can result in undefined behavior. HTC status and control is provided through F3x64.
The PROCHOT_L pin acts as both an input and as an open-drain output. As an output, PROCHOT_L is driven low to indicate that the HTC-active state has been entered due to an internal condition, as described by the following text. The minimum assertion and deassertion time for PROCHOT_L is 15 ns.
The processor enters the HTC-active state if all of the following conditions are true:
F3xE8[HtcCapable]=1
F3x64[HtcEn]=1
PWROK=1
THERMTRIP_L=1
The processor is not in the C3 ACPI state.
and any of the following conditions are true:
Tctl is greater than or equal to the HTC temperature limit (F3x64[HtcTmpLmt]).
PROCHOT_L=0
The processor exits the HTC-active state when all of the following are true:
Tctl is less than the HTC temperature limit (F3x64[HtcTmpLmt]).
Tctl has become less than the HTC temperature limit (F3x64[HtcTmpLmt]) minus the HTC hysteresis limit (F3x64[HtcHystLmt]) since being greater than or equal to the HTC temperature limit (F3x64[HtcTmpLmt]).
PROCHOT_L=1.
The default value of the HTC temperature threshold (Tctl_max) is specified in the Power and Thermal Datasheet.
2.10.3.2 Software Thermal Control (STC)
STC is controlled by [The Software Thermal Control (STC) Register] F3x68. This register provides a software-controlled mechanism to alter power consumption based on temperature. When the processor control temperature (Tctl; see section 2.10.1 [The Tctl Temperature Scale] on page 110) exceeds the temperature threshold specified by F3x68[StcTmpLmt], then the processor enters the STC thermal zone. When it subsequently drops below F3x68[StcTmpLmt] minus F3x68[StcHystLmt], the processor exits the STC thermal zone. F3x68 controls whether interrupts or special bus cycles (which may be converted into interrupts by the chipset) are generated when the processor transitions into and out of the STC thermal zone. The interrupt handler may take an action to alter power consumption or alter the level of external cooling.
One way that software may reduce power is to program the processor to enter the STC-active state. This is like the HTC-active state, however PROCHOT_L is not asserted. The processor enters the STC-active state if F3x68[StcPstateEn]=1. While in the STC-active state, the processor limits the performance to the P-state specified by [The Software Thermal Control (STC) Register] F3x68[StcPstateLimit]; See section 2.4.2 [P-states]
on page 31.
2.10.3.3 THERMTRIP
If the processor supports the THERMTRIP state (as specified by [The Thermtrip Status Register] F3xE4[ThermtpEn] or CPUID Fn8000_0007[TTP], which are the same) and the temperature approaches the point at which the processor may be damaged, the processor enters the THERMTRIP state. The THERMTRIP function is enabled after cold reset (after PWROK asserts and RESET_L deasserts). It remains enabled in all other processor states, except during warm reset (while RESET_L is asserted). The THERMTRIP state is characterized as follows:
The THERMTRIP_L signal is asserted.
Nearly all clocks are gated off to reduce dynamic power.
A low-value VID is generated.
In addition, the external chipset is expected to place the system into the S5 ACPI state (power off) if THERMTRIP_L is detected to be asserted.
A cold reset is required to exit the THERMTRIP state.
Quote:
Originally Posted by K10 Temperature Resolution
The processor measures temperature to 1/2-degree C resolution. However, temperature is reported through Tctl with 1/8th-degree resolution. The translation to finer resolution is accomplished using slew rate controls in this register. These specify how quickly Tctl steps to the measured temperature in 1/8th-degree steps. Separate controls are provided for measured temperatures that are higher and lower than Tctl. The per-step timer counts as long as the measured temperature stays either above or below Tctl; each time the measured temperature flops to the other side of Tctl, the step timer resets. If, for example, step times are enabled in both directions, Tctl=62.625, and the measured temperature keeps jumping quickly between 62.5 and 63.0, then (assuming the step times are long enough) Tctl would not change; however, once the measured temperature settles on one side of Tctl, Tctl can step toward the measured temperature.
Also it seems NB Speed can also be dropped in low power states using DID (?):
Quote:
F3xD4 [30:28] NbClkDiv: NB clock divisor. Read-write. Cold reset: value varies by product.
Specifies the NB CLK divisor associated with [The ACPI Power State Control Registers] F3x[84:80][NbLowPwrEn]. This divisor is applied while LDTSTOP is asserted if the corresponding core CLK divisor, F3x[84:80][ClkDivisor], is set to turn off clocks or if NBClkDivApplyAll=1; otherwise, the divisor specified by F3x[84:80][ClkDivisor] is applied. This divisor is relative to the current NB FID frequency, or:
200 MHz * (4 + F3xD4[NbFid]).
If MSRC001_00[68:64][NbDid] of the current P-state indicates a divisor that is lower than specified by this field, then no NB frequency change is made when entering the low-power state associated with this register (i.e., if this field specifies a divide-by 1 and the DID is divide-by 2, then the divisor remains 2 while in the low-power state). This field is encoded as follows:
Bits Divisor Bits Divisor
000b Divide-by 1. 100b Divide-by 16.
001b Divide-by 2. 101b Reserved.
010b Divide-by 4. 110b Reserved.
011b Divide-by 8. 111b Reserved.
BIOS should set this field to 100b
Quote:
2.9.2 CPU Cores and Downcoring
Each node supports 1, 2, 3, or 4 CPU cores as follows:
The number of cores supported by the node is specified by F3xE8[CmpCap].
CPU cores may be downcored (removed) by F3x190[DisCore[3:0]] through a warm reset. This may be useful in that CPU cores that are determined to be bad may be removed from operation. Based on F3xE8[Cmp-Cap], DisCore[0] applies to a single-core node; DisCore[1:0] apply to a dual-core node; DisCore[2:0] apply to a 3-core node; DisCore[3:0] apply to a 4-core node.
F3x190[DisCore] affects CPUID Fn8000_0008_ECX[NC].
Software is required to use F3x190[DisCore[3:0]] as follows:
1, 2, 3 or 4 cores must be enabled on each node(0-core configurations are not allowed).
Setting bits corresponding to CPU cores that are not present results in undefined behavior.
Once a core has been removed, it cannot be added back without a cold reset.
If the number of cores in the system is changed, then F0x60[CpuCnt] in all nodes must be updated to reflect the new value after the warm reset.
The CPU core number, CpuCoreNum, is provided to SW running on each core through CPUID Fn0000_0001_EBX[LocalApicId] and APIC20[ApicId], formatted based on the state of MSRC001_001F[InitApicIdCpuIdLo]; CpuCoreNum also affects F0x68[Cpu1En] and F0x168[Cpu3En and Cpu2En]. CpuCoreNum, varies as the lowest integers from 0 to 3, based on the number of enabled cores;
e.g., a 4-core node with 1 core disabled results in cores reporting CpuCoreNum values of 0, 1, and 2 regardless of which core is disabled. Here are all the possible downcore combinations:
A 4-core node with 0 cores disabled. A 3-core node with 0 cores disabled.
A 4-core node with 1 core disabled. A 3-core node with 1 core disabled.
A 4-core node with 2 cores disabled. A 3-core node with 2 cores disabled.
A 4-core node with 3 cores disabled. A 2-core node with 0 cores disabled.
A 1-core node with 0 cores disabled. A 2-core node with 1 core disabled.
The boot core is always the core reporting CpuCoreNum = 0.
Some legacy operating systems do not support three core processors. The BIOS should support a user configurable option to disable one core in a three core processor for legacy operating system support.
Achim, have you tried limiting CPU temp using STC? (changing the value manually)
BTW, see if you can spot something incorrectly affirmed here: http://www.xbitlabs.com/articles/cpu...md-k10_10.html ;)
Check these two articles:
http://money.cnn.com/2008/04/07/tech...tune/index.htm
http://www.eetimes.com/news/latest/s...leID=207100361
