DFI first DDR3 motherboard, UT X48-T3R Heatsink by Thermalright

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06-14-2008, 03:12 PM
Praz

Quote:

Originally Posted by karlpox

yep just borrowed his rams (ocz reaperx 2x2gb ddr3-1333) but still doesnt work. any other options on what i can with my problem??

You need ram that will not boot at CAS 7 from the SPD. The ReaperX boots at CAS 7.
06-15-2008, 05:36 PM
ACE76

Quote:

Originally Posted by Clunk

Here :)

the last run was just to see how high it would go with the 9.5 multi at 1:2. I was hoping to get to 500/2000 but i was just short of that at 488/1952.

Going to try with a lower multi and see what I can get :)

That's some excellent work Clunk! I hope when my phase system is completed, that you'll help me out with my 9770 and OCZ Flex II 8-8-8 kit on this mobo...I believe it's the same memory as the Platinum EB that you used but since it has better cooling, they released it with a tighter timing...I wonder if 2.1ghz would be possible with water cooling on the memory.
06-16-2008, 11:18 AM
Clunk

Thanks :)

Not sure about the memory yet, not managed to hit the rated speed with any stability yet, so can't comment there.

I just wish they would hurry up with a 500fsb+-enabled-non-alpha-publically-available-BIOS so I can move on with the review :lol:
06-17-2008, 01:35 AM
fireice2

@karl

Hows the Hotflashed BIOS chip? :D Hot flashing really comes in handy. hehehe Hope you enjoy your new toy.
06-20-2008, 07:27 AM
Clunk

New BIOS if anyone is in need. :up:
06-22-2008, 06:34 AM
Praz

LP UT X48-T3RS, E8400, 480x8.5, ReaperX 1333MHz, Post 1 Of 3

E8400
DFI LP UT X48-T3RS, 06/09 BIOS
480x8.5, Memory 1600MHz
2x2GB OCZ PC3-10666 1333MHz ReaperX
XFX8800 GTS (G92)
tRD - 8.5, Memset Misreads The Value When Set Manually
Memory Speed - 1600MHZ, CPU-Z Misreports The Divider
Yellow Slots Used For Memory

click for larger image
http://www.edgeofstability.com/image...ios/main_s.jpg http://www.edgeofstability.com/image...ios/volt_s.jpg

click for larger image
http://www.edgeofstability.com/image...s/dram_1_s.jpg http://www.edgeofstability.com/image...s/dram_2_s.jpg

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http://www.edgeofstability.com/image.../clock_1_s.jpg http://www.edgeofstability.com/image.../clock_2_s.jpg

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http://www.edgeofstability.com/image...os/phase_s.jpg http://www.edgeofstability.com/image.../feature_s.jpg

Code:

CPU Feature Page Thermal Management Control................Enabled PPM (EIST) Mode...........................Disabled Limit CPUID MaxVal........................Disabled CIE Function..............................Disabled Virtualization Technology.................Disabled Core Multi-Processing.....................Enabled Main BIOS Page Exist Setup Shutdown......................Mode 2 Shutdown After AC Loss....................Disabled O. C. Fail Retry Counter..................0 CLOCK VC0 Divider.........................Auto CPU Clock Ratio...........................8.5x CPU N/2 Ratio.............................Enabled CPU Clock.................................480 MHz Boot Up Clock.............................Auto CPU Clock Amplitude.......................800mV CPU Clock0 Skew...........................0ps CPU Clock0 Skew...........................0ps DRAM Speed................................400/1333 PCIE Clock................................100MHz PCIE Slot Config..........................1X 1X CPU Spread Spectrum.......................Disabled PCIE Spread Spectrum......................Disabled SATA Spread Spectrum......................Disabled Voltage Setting Page CPU VID Control...........................1.34375V CPU VID Special Add Limit.................Enabled CPU VID Special Add.......................Auto DRAM Voltage Control......................1.837V SB Core/CPU PLL Voltage...................1.510V NB Core Voltage...........................1.543V CPU VTT Voltage...........................1.144V VCore Droop Control.......................Disabled Clockgen Voltage Control..................3.45V GTL+ Buffers Strength.....................Strong Host Slew Rate............................Weak GTL REF Voltage Control...................Disabled CPU GTL 1/2 REF Volt......................113 CPU GTL 0/3 REF Volt......................100 North Bridge GTL REF Volt ................100 DRAM Timing Page Enhance Data Transmitting.................Fast Enhance Addressing........................Fast T2 Dispatch...............................Disabled Clock Setting Fine Delay..................Listed Below CAS Latency Time (tCL)....................7 RAS# to CAS# Delay (tRCD).................6 RAS# Precharge (tRP)......................6 Precharge Delay (tRAS)....................20 All Precharge to Act......................Auto REF to ACT Delay (tRFC)...................Auto Performance Level.........................9 Read Delay Phase Adjust...................Listed Below MCH ODT Latency...........................Auto Write to PRE Delay (tWR)..................Auto Rank Write to Read (tWTR).................Auto ACT to ACT Delay (tRRD)...................Auto Read to Write Delay (tRDWR)...............Auto Ranks Write to Write (tWRWR)..............Auto Ranks Read to Read (tRDRD)................Auto Ranks Write to Read (tWRRD)...............Auto Read CAS# Precharge (tRTP)................Auto ALL PRE to Refresh........................Auto Read Delay Phase Adjust Page Channel 1 Phase 0 Pull-In.................Enabled Channel 1 Phase 1 Pull-In.................Enabled Channel 1 Phase 2 Pull-In.................Enabled Channel 1 Phase 3 Pull-In.................Enabled Channel 1 Phase 4 Pull-In.................Enabled Channel 2 Phase 0 Pull-In.................Auto Channel 2 Phase 1 Pull-In.................Auto Channel 2 Phase 2 Pull-In.................Auto Channel 2 Phase 3 Pull-In.................Auto Channel 2 Phase 4 Pull-In.................Auto Clock Setting Fine Delay Page DRAM Default Skew Model...................Model 3 Fine Delay Step Degree....................5ps Ch1 Clock Crossing Setting................Auto DIMM 1 Clock fine delay...................Current 489ps DIMM 2 Clock fine delay...................Current 489ps DIMM 1 Control fine delay.................Current 434ps DIMM 2 Control fine delay.................Current 473ps Ch 1 Command fine delay...................Current 205ps Ch2 Clock Crossing Setting................Auto DIMM 3 Clock fine delay...................Current 686ps DIMM 4 Clock fine delay...................Current 686ps DIMM 3 Control fine delay.................Current 607ps DIMM 4 Control fine delay.................Current 654ps Ch 2 Command fine delay...................Current 182ps Ch1Ch2 CommonClock Setting................Auto Ch1 RDCAS GNT-Chip Delay..................Auto Ch1 WRCAS GNT-Chip Delay..................Auto Ch1 Command to CS Delay...................Auto Ch2 RDCAS GNT-Chip Delay..................Auto Ch2 WRCAS GNT-Chip Delay..................Auto Ch2 Command to CS Delay...................Auto Common CMD to CS Timing...................Auto
06-22-2008, 06:36 AM
Praz

LP UT X48-T3RS, E8400, 480x8.5, ReaperX 1333MHz, Post 2 Of 3

XP SP3

click for larger image
http://www.edgeofstability.com/image..._occt_xp_s.jpg

click for larger image
http://www.edgeofstability.com/image..._3d06_xp_s.jpg

http://www.edgeofstability.com/image..._crysis_xp.jpg http://www.edgeofstability.com/image...600_ut3_xp.jpg

3dx Max w/V-ray
Time to render: 14min 08sec

click for larger image
http://www.edgeofstability.com/image...chmark_680.jpg

click for larger image
http://www.edgeofstability.com/image...erest_xp_s.jpg
06-22-2008, 06:37 AM
Praz

LP UT X48-T3RS, E8400, 480x8.5, ReaperX 1333MHz, Post 3 Of 3

Vista 64 Bit SP1

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http://www.edgeofstability.com/image..._occt_64_s.jpg

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http://www.edgeofstability.com/image...dmark_64_s.jpg

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http://www.edgeofstability.com/image...mark_van_s.jpg

click for larger image
http://www.edgeofstability.com/image...0_pcmark_s.jpg

http://www.edgeofstability.com/image..._crysis_64.jpg http://www.edgeofstability.com/image...600_ut3_64.jpg

3dx Max w/V-ray
Time to render: 15min 30sec

click for larger image
http://www.edgeofstability.com/image...chmark_680.jpg

click for larger image
http://www.edgeofstability.com/image...erest_64_s.jpg
06-22-2008, 06:52 AM
quake6

Max FSB? Nice bench's
06-22-2008, 07:02 AM
Praz

Quote:

Originally Posted by quake6

Max FSB? Nice bench's

Thanks. Don't know about the FSB yet. Haven't even had any 1x2GB sticks in it. Testing a couple more 2x2GB sets then will find out what it can do with 8GB. After that will look at 1x2GB and max FSB. The BIOS is still being tuned also. Oskar is sending several alphas versions each say. The above screenshots were done with an official version.
06-22-2008, 01:20 PM
Roger_D25

Great work Praz, thanks for posting! I had to keep remembering that your running 2 x 2GB moduls, not 2x 1GB! With that said very impressive results! I'm curious about your "Read Delay Phase Adjust" settings. I've yet to play with them much and when I have I couldn't notice any significant benchmark results or stability results. Is there any chance you would share why you ended up changing all the "Channel 1" settings to "Enabled", was it for stability or performance? Also in the BIOS screenshots you posted it looks like you have "T2 Dispatch" setting set to Disabled, but in your BIOS Settings Code you have it listed as "Auto". For the results you have posted did you have the BIOS "T2 Dispatch" setting set to "Disabled" or "Auto". Thanks again Praz for your help! Like you I'm still working with 06/09, although I've tried a couple of the new Beta's released recently.
06-22-2008, 01:32 PM
Praz

Fixed T2 Dispatch. With 2x2GB sticks it needs to be disabled. Depending on speed, both Enhance Data Transmitting and Enhance Addressing may also have to be set to Disabled. Everest shows a gain with tRD set at 8 1/2 compared to 9. The board can do a straight 8 but it requires quite a bit of increase to NB voltage to hold stability.
06-23-2008, 05:17 PM
Praz

LP UT X48-T3RS, E8400, 500x8, Platinum EB 1600MHz, Post 1 Of 3

DFI LP UT X48-T3RS, 06/09 BIOS
E8400
500x8, Memory 1666MHz
2x2GB OCZ PC3-12800 1600MHz Platinum EB
XFX8800 GTS (G92)
tRD - 8.5, Memset Misreads The Value When Set Manually
Memory Speed - 1666MHZ, CPU-Z Misreports The Divider
Yellow Slots Used For Memory

click for larger image
http://www.edgeofstability.com/image...ios/main_s.jpg http://www.edgeofstability.com/image...ios/volt_s.jpg

click for larger image
http://www.edgeofstability.com/image...s/dram_1_s.jpg http://www.edgeofstability.com/image...s/dram_2_s.jpg

click for larger image
http://www.edgeofstability.com/image.../clock_1_s.jpg http://www.edgeofstability.com/image.../clock_2_s.jpg

click for larger image
http://www.edgeofstability.com/image...os/phase_s.jpg http://www.edgeofstability.com/image.../feature_s.jpg

Code:

CPU Feature Page Thermal Management Control................Enabled PPM (EIST) Mode...........................Disabled Limit CPUID MaxVal........................Disabled CIE Function..............................Disabled Virtualization Technology.................Disabled Core Multi-Processing.....................Enabled Main BIOS Page Exist Setup Shutdown......................Mode 2 Shutdown After AC Loss....................Disabled O. C. Fail Retry Counter..................0 CLOCK VC0 Divider.........................Auto CPU Clock Ratio...........................8x CPU N/2 Ratio.............................Disabled CPU Clock.................................500 MHz Boot Up Clock.............................Auto CPU Clock Amplitude.......................800mV CPU Clock0 Skew...........................0ps CPU Clock0 Skew...........................0ps DRAM Speed................................400/1333 PCIE Clock................................100MHz PCIE Slot Config..........................1X 1X CPU Spread Spectrum.......................Disabled PCIE Spread Spectrum......................Disabled SATA Spread Spectrum......................Disabled Voltage Setting Page CPU VID Control...........................1.31255V CPU VID Special Add Limit.................Enabled CPU VID Special Add.......................Auto DRAM Voltage Control......................1.855V SB Core/CPU PLL Voltage...................1.510V NB Core Voltage...........................1.630V CPU VTT Voltage...........................1.325V VCore Droop Control.......................Disabled Clockgen Voltage Control..................3.45V GTL+ Buffers Strength.....................Strong Host Slew Rate............................Strong GTL REF Voltage Control...................Disabled CPU GTL 1/2 REF Volt......................113 CPU GTL 0/3 REF Volt......................100 North Bridge GTL REF Volt ................100 DRAM Timing Page Enhance Data Transmitting.................Fast Enhance Addressing........................Fast T2 Dispatch...............................Disabled Clock Setting Fine Delay..................Listed Below CAS Latency Time (tCL)....................7 RAS# to CAS# Delay (tRCD).................6 RAS# Precharge (tRP)......................6 Precharge Delay (tRAS)....................20 All Precharge to Act......................Auto REF to ACT Delay (tRFC)...................Auto Performance Level.........................9 Read Delay Phase Adjust...................Listed Below MCH ODT Latency...........................Auto Write to PRE Delay (tWR)..................Auto Rank Write to Read (tWTR).................Auto ACT to ACT Delay (tRRD)...................Auto Read to Write Delay (tRDWR)...............Auto Ranks Write to Write (tWRWR)..............Auto Ranks Read to Read (tRDRD)................Auto Ranks Write to Read (tWRRD)...............Auto Read CAS# Precharge (tRTP)................Auto ALL PRE to Refresh........................Auto Read Delay Phase Adjust Page Channel 1 Phase 0 Pull-In.................Enabled Channel 1 Phase 1 Pull-In.................Enabled Channel 1 Phase 2 Pull-In.................Enabled Channel 1 Phase 3 Pull-In.................Enabled Channel 1 Phase 4 Pull-In.................Enabled Channel 2 Phase 0 Pull-In.................Auto Channel 2 Phase 1 Pull-In.................Auto Channel 2 Phase 2 Pull-In.................Auto Channel 2 Phase 3 Pull-In.................Auto Channel 2 Phase 4 Pull-In.................Auto Clock Setting Fine Delay Page DRAM Default Skew Model...................Model 3 Fine Delay Step Degree....................5ps Ch1 Clock Crossing Setting................Auto DIMM 1 Clock fine delay...................Current 489ps DIMM 2 Clock fine delay...................Current 489ps DIMM 1 Control fine delay.................Current 434ps DIMM 2 Control fine delay.................Current 473ps Ch 1 Command fine delay...................Current 560ps Ch2 Clock Crossing Setting................Auto DIMM 3 Clock fine delay...................Current 686ps DIMM 4 Clock fine delay...................Current 686ps DIMM 3 Control fine delay.................Current 607ps DIMM 4 Control fine delay.................Current 654ps Ch 2 Command fine delay...................Current 639ps Ch1Ch2 CommonClock Setting................Auto Ch1 RDCAS GNT-Chip Delay..................Auto Ch1 WRCAS GNT-Chip Delay..................Auto Ch1 Command to CS Delay...................Auto Ch2 RDCAS GNT-Chip Delay..................Auto Ch2 WRCAS GNT-Chip Delay..................Auto Ch2 Command to CS Delay...................Auto Common CMD to CS Timing...................2N

click for larger image
http://www.edgeofstability.com/image...6_memset_s.jpg
06-23-2008, 05:18 PM
Praz

LP UT X48-T3RS, E8400, 500x8, Platinum EB 1600MHz, Post 2 Of 3

XP SP3

click for larger image
http://www.edgeofstability.com/image..._occt_xp_s.jpg

click for larger image
http://www.edgeofstability.com/image..._3d06_xp_s.jpg

http://www.edgeofstability.com/image..._crysis_xp.jpg http://www.edgeofstability.com/image...6eb_ut3_xp.jpg

3dx Max w/V-ray
Time to render: 14min 26sec

click for larger image
http://www.edgeofstability.com/image...chmark_680.jpg

click for larger image
http://www.edgeofstability.com/image...erest_xp_s.jpg
06-23-2008, 05:20 PM
Praz

LP UT X48-T3RS, E8400, 500x8, Platinum EB 1600MHz, Post 3 Of 3

Vista 64 Bit SP1

click for larger image
http://www.edgeofstability.com/image..._occt_64_s.jpg

click for larger image
http://www.edgeofstability.com/image...dmark_64_s.jpg

click for larger image
http://www.edgeofstability.com/image...mark_van_s.jpg

click for larger image
http://www.edgeofstability.com/image...6_pcmark_s.jpg

http://www.edgeofstability.com/image..._crysis_64.jpg http://www.edgeofstability.com/image...6eb_ut3_64.jpg

3dx Max w/V-ray
Time to render: 15min 43sec

click for larger image
http://www.edgeofstability.com/image...chmark_680.jpg

click for larger image
http://www.edgeofstability.com/image...erest_64_s.jpg
06-23-2008, 05:53 PM
Riggs

Nice results! I should have forked out the extra few dollars for this board instead of my DK x38.
06-24-2008, 04:40 PM
disruptfam

nice...!!! i want one but i want to wait for the x58 tr3 :)
06-24-2008, 06:01 PM
Praz

Thanks guys. Some OCZ 1600EB 2x1GB sticks using the 06/09 BIOS. Just a quick run to get some base settings.

click for larger image
http://www.edgeofstability.com/image...1/501_pi_s.jpg

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http://www.edgeofstability.com/image...501_ever_s.jpg
06-24-2008, 07:28 PM
AriciU

So, this board will not boot, out of the box, with the Corsair 1600C7DHX ? :(
06-24-2008, 07:32 PM
Praz

Quote:

Originally Posted by AriciU

So, this board will not boot, out of the box, with the Corsair 1600C7DHX ? :(

It depends on what the SPD is programmed to boot at not the actual rating of the ram.
06-24-2008, 07:36 PM
AriciU

I see. I would greatly appreciate for anyone that's using that ram to check the SPD ratings. It would suck to spend ~400EUR and just look at the damn box. :)
06-24-2008, 07:50 PM
Praz

Ask Corsair what CAS value the ram will boot with.
06-24-2008, 08:00 PM
AriciU

Just sent them an email. Maybe DFI will address that issue though untill the 8th when i will probably buy the motherboard.
06-25-2008, 03:40 AM
Praz

The issue is already addressed, The 06/09 and later BIOS' will boot regardless of ram used. But there are still some boards for sale with an older BIOS.
06-25-2008, 07:13 PM
disruptfam

http://www.iamxtreme.net/andre/X48-T3R/15.JPG

is it just the x48 tr3 that has those thermalright heatsinks?

how about the x48 tr2?

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