Originally Posted by
rosco
Absolutely not. A silicon die is not a very good thermal conductor (bulk silicon ~148 W/m.K and far worse for others materials used to create transistors structures, etc.). Thermal gradient within the die can achieve 20~40+ °C between the hottest and the coldest point, depending of the load. That's why a die presents what we call 'hot spots' because there are hotter than the rest of the die (more power density such ALU or fetch units for instance) and they are the major problem to cool the chip and ensure reliability. Die temperature map is and won't be uniform at all, ever !
On a dualcore, it's clearly seen. Load only one core with TAT for instance and look values reported by the DTS sensors, there will be ~4-7 °C between them (depending of cooling system) and however the sensors are only ~5 mm far from each other. According to you, the sensors should be at the same temperature, which is nonphysical. There's always a thermal gradient when heat has to travel through materials. The worse the material is, the higher the gradient will be at a given distance, Fourier law. CPU TEMP provided by the third thermal diode don't have to be the same than DTS TEMP, it's located between the 2 DTS sensors but in a 'colder' place (results are affected by mobo circuitry unfortunately, but a external system could normally be used to calibrate and use it like on AMD CPU).
Nothing is linear here, you can't guess the difference between sensors, that's why temperature difference between them is evolving for each situation (idle/load but what load...). Intel already showed the large deviation between Tj provided by DTS and Tcpu provided by the third sensor depending of die loading map (power map more precisely), there's no relation at all between them ! We can see Tcpu like a 'mean' temperature if we want, that's all.