!!!The Ultimate K8L Thread 2007 & Beyond!!!

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Originally Posted by Lightman

Some interesting bits:


Source:
http://www.edn.com/article/CA6415782.html?partner=enews

Enjoy!

:)

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95C ... this has gotta be a typo....

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Originally Posted by JumpingJack

95C ... this has gotta be a typo....

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No it's not a typo. They are modeling core frequency at high temperatures because most servers are running in tight blade cases, people in Africa want to use air cooling :p:, etc.
To be serious I think it is industrial standard for measurements. Look at speed modeling of other CPUs like this Intel 80core monster. It's speed was modeled at the same 95C temperature.

This of course has good prospects for us because if you will keep this core at around 65C then @1.15V you can go a bit higher than 2.8GHz on Quad core. :D . Add some volts and job done! 3GHz should be easy.... :woot:

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Originally Posted by brentpresley

Keep on flamebaiting and you will go the way of Serge84. :fact:

Does it make your e-Pen_is bigger to throw barbs when you can't come up with any facts to refute my arguments. Only 2 year olds throw temper tantrums.

He didn't violate NDA to me, just confirmed for me what my other friend at DOE had already said.

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Its not a fact, lol its only a delay. XD :fact: And friends tend to lend you things.

Anyways back on topic...
Please by all means show us the K10 your friend has? We would all love to see. I mean if he really did show you these performance numbers why don't you/he post them? Any kind of numbers. If your being truthful with all your arguments please state/show more facts on what your saying. Not trying to flame or anything because my statment is not stated as such. Only your not the kind of person that backs up their clams very well, we all just want to know more. Thats what this thread is all about after all. :toast:

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Originally Posted by Lightman

No it's not a typo. They are modeling core frequency at high temperatures because most servers are running in tight blade cases, people in Africa want to use air cooling :p:, etc.
To be serious I think it is industrial standard for measurements. Look at speed modeling of other CPUs like this Intel 80core monster. It's speed was modeled at the same 95C temperature.

This of course has good prospects for us because if you will keep this core at around 65C then @1.15V you can go a bit higher than 2.8GHz on Quad core. :D . Add some volts and job done! 3GHz should be easy.... :woot:

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These processors can get hot. Opterons are built to take this heat. Server consissions range from 70C to 80C+ temps usoully in a standard blade. Some of us don't know about server condissions, but the ones that do should be taken word for word. It gets very hot in a blade server more then most like. lol Besides cpus are not that fragile. Xeons and opterons alike you would be amazed the punisment they can take in testing as well as 24/7 use.

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Originally Posted by doompc

All CPUs speed up in 64 bits due to the larger amout of registers and the standard SSE2 instructions.
But Core2 does not speed up as much as K8 since MacroFusion doesn't work in long mode.

On SSE execution K10 has little advantage.
Core2 has 3 SSEs plus one load and one store units.
K8 has 3 FPUs (that do SSE) plus the load/store unit that do two loads/stores per cycle, on K10 the FPUs are widened to 128 bit so it can do 3 128 bit SSE per cycle plus 2 load/stores.
So Core2 does 3 SSE, 1 load and 1 store. K10 does 3 SSE, 1 load and 1 store or 2 loads or 2 stores.
http://www.xbitlabs.com/articles/cpu...amd-k8l_5.html

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Great find.

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Originally Posted by LOE

are you sure? :nono: C2D can process one 128bit sse instruction per cycle, do you mean pentium has a 21.33 (128/6) bit SSE engine :rofl:

Pentium D needs 2 cycles to execute one 128 bit sse instruction.. it has a 64bit engine

core 2 duo has 2x the SSE throughoutput of pentium



Yes it is missing in minesweeper, but every serious app supports SSE, there are even apps that DO NOT RUN if they don't detect atleast SSE

One of the reason c2d is 50-100% faster than pentium clock for clock is it's double SSE throughoutput - check apps that render 3d, or encode video

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I took this as fallows... :ROTF: :wierd: :rofl:

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Originally Posted by accord99

But it's not slower, sometimes its faster, sometimes its slower depending on the application, just like the K8. Overall, it still remains the fastest 64-bit x86 processor available today.


We see a one or two unrealistic scenarios where this happens and requires specific situations that benefit from the Quad FX's additional memory controller. However, in a single-socket system, the desktop versions of Barcelona will only have 1 memory controller and 12.8GB/s of memory bandwidth.

Most other heavy multi-threaded scenarios have the QX6700 beating the Quad FX just as easily as it does in single-threaded scenarios.


A C2D can execute 1 128-bit multiply, 1 128-bit add plus a load, store and jump in the same cycle.

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I agree, only K10 has dual memory controllers in the specs. According to previous data in the past threads about K10. Current bandwidth on AM2 is 20GB/s it will nearly be 3x of that bandwidth wise. Double that on memory bandwidth. According to dalytech was it...

http://www.channelinsider.com/print_...ls/191008.aspx

Quad-core parts and other Revision H parts are rumored to have two 64-bit independent memory controllers each with its own physical address space thus giving an opportunity to better utilize the available bandwidth in case of random memory accesses occurring in heavily multi-threaded environment. This approach is in a contrary to the previous "interleaved" design, where the two 64-bit data channels are bounded to a single common address space. It will be the first single-chip implementation of the non-uniform memory access architecture.

http://www.realworldtech.com/page.cf...0206035626&p=1

http://www.realworldtech.com/page.cf...0206035626&p=2

http://www.google.com/search?hl=en&q...rs&btnG=Search

Just some more info on K10 in previous threads. But you all should really read that thread to get the lowdown on K10. I should post a link on the front of the page as a continuation. And not constently rehunting for data having ppl acting like it never existed. Sometimes its silly for somebody to have to repeat themselfs. XD

http://www.xtremesystems.org/forums/...d.php?t=117702

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Originally Posted by LOE

are you sure? :nono: C2D can process one 128bit sse instruction per cycle, do you mean pentium has a 21.33 (128/6) bit SSE engine :rofl:

Pentium D needs 2 cycles to execute one 128 bit sse instruction.. it has a 64bit engine

core 2 duo has 2x the SSE throughoutput of pentium



Yes it is missing in minesweeper, but every serious app supports SSE, there are even apps that DO NOT RUN if they don't detect atleast SSE

One of the reason c2d is 50-100% faster than pentium clock for clock is it's double SSE throughoutput - check apps that render 3d, or encode video

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Dont try and mix numbers in your favour. Core got 1 SSE port thats 64bit. Core 2 got 3 SSE ports thats 128bit. Yet Core at same FSB/Clock aint much slower than Core 2. And thats with all the rest of the improvements too.

http://techreport.com/reviews/2006q3/core2/index.x?pg=2

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Originally Posted by Grayfox84

I agree, only K10 has dual memory controllers in the specs. According to previous data in the past threads about K10. Current bandwidth on AM2 is 20GB/s it will nearly be 3x of that bandwidth wise. Double that on memory bandwidth. According to dalytech was it...

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AM2's memory bandwidth is 12.8GB/s. If you plug in a Barcelona core into an AM2, that's all you get since there is physically only two channels connecting the memory to the socket.

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http://www.channelinsider.com/print_...ls/191008.aspx

Quad-core parts and other Revision H parts are rumored to have two 64-bit independent memory controllers each with its own physical address space thus giving an opportunity to better utilize the available bandwidth in case of random memory accesses occurring in heavily multi-threaded environment. This approach is in a contrary to the previous "interleaved" design, where the two 64-bit data channels are bounded to a single common address space. It will be the first single-chip implementation of the non-uniform memory access architecture.

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Intel's current DDR2 memory controllers are already this way.

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Originally Posted by accord99

AM2's memory bandwidth is 12.8GB/s. If you plug in a Barcelona core into an AM2, that's all you get since there is physically only two channels connecting the memory to the socket.


Intel's current DDR2 memory controllers are already this way.

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Yeap! At the rated PC6400 speed of course. At the moment AMD and few other companies are trying to push higher memory specification through JEDEC. I heard PC8500 is target for them.
This would allow DESKTOP version of AMD Quad to get 17GB/s memory bandwidth...

Of course servers are different animals and I think maximum we will see would be PC6400 Registered dimms (DDR-II 800MHz :) )

Regarding SSE2, I still expect Core 2 to have edge over the K10, as it has a higher peak theoretical throughput..

Core 2 can issue a max of 6 SSE instructions per cycle, while the K10 can do 3.

Ofocurse, there are other factors involved other than peak SIMD throughput, like latency and memory bandwidth, and the K10 will have the edge there.

But not enough to trounce C2D IMO.

As for INT, C2D should still maintain a healthy lead as the C2D is a beast in INT. It will be interesting to see which processor holds the performance crown for gaming, as games tend to be far more INT based than FP.

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Originally Posted by Shintai

Dont try and mix numbers in your favour. Core got 1 SSE port thats 64bit. Core 2 got 3 SSE ports thats 128bit. Yet Core at same FSB/Clock aint much slower than Core 2. And thats with all the rest of the improvements too.

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Core Duo has 2 64-bit SSE2 ports, not 1.

As for the closer than expected performance delta between C2D and CD, I put it down to two things:

1) Merom is FSB limited at 667, far moreso than Yonah.

2) Yonah was already a very efficient high IPC processor. Actually, it was even faster than the K8 clock for clock in everything but FP intensive apps.

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Originally Posted by doompc

All CPUs speed up in 64 bits due to the larger amout of registers and the standard SSE2 instructions.
But Core2 does not speed up as much as K8 since MacroFusion doesn't work in long mode.

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I'm willing to bet this will be addressed in Penryn.

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On SSE execution K10 has little advantage.
Core2 has 3 SSEs plus one load and one store units.
K8 has 3 FPUs (that do SSE) plus the load/store unit that do two loads/stores per cycle, on K10 the FPUs are widened to 128 bit so it can do 3 128 bit SSE per cycle plus 2 load/stores.
So Core2 does 3 SSE, 1 load and 1 store. K10 does 3 SSE, 1 load and 1 store or 2 loads or 2 stores.
http://www.xbitlabs.com/articles/cpu...amd-k8l_5.html

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I don't know how accurate this information is. As far as I know, the K10 can issue 2 SSE operations, and one SSE MOV per cycle in the floating point store pipe.

So thats three instructions peak. Core 2 on the other hand, can potentially do double the K10's SSE issue rate.

Carfax, it's not clear if the FMISC unit (that do FLOAD in K8) will be widened to 128 bit. If not could not do 1x 128 bit SSE Load per cycle.

Core2 can theoricaly issue 6x micro-ops per cycle, and it decodes a maximum 2+3 instructions, but it fetches 16 Byte, that's only 128 bits. With the data on bufer waiting to be decoded it may decode an average 3 instructions per cycle.
I bet the 32 Byte instruction fetch will keep K10's FPUs much busier than Conroe's.

Doompc, do you think it's possible that Intel could implement a 32 byte instruction fetch in Penryn with the extra transistors?

How radical a change would it be to do something like that?

Carfax, I think so, but Intel has not commented anything on this subject.

LOE, we don't have info on that. But even if FMISC is still 64 bit the decoder may simply route the SSE Loads to the Load/Store unit.

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Originally Posted by MAS

We've already had confirmation that 40% overall is simply not happening
Randy Allen and Patrik Patla (AMD directors) told us about 40per cent, and suddenly brentpresley appears and tells us


look better at the picture

40 % advantage is for rough multitasking environment
10 % is for single-threaded appl.

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Weren't those the same folks who said the Conroe Tests were Bogus and rigged? So why should we believe them?

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Originally Posted by Carfax

Regarding SSE2, I still expect Core 2 to have edge over the K10, as it has a higher peak theoretical throughput..

Core 2 can issue a max of 6 SSE instructions per cycle, while the K10 can do 3.

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I'm sorry to say that you've got a messup.
1) C2D has 6 uOps per cycle. K10 has 3 SSE per cycle. See the difference?

only scalar SSE operations are single uOps while the vector operations are typically 2-4 uOps.

Don't believe? Read here...

just in case you did not know: mOps fusion - old K8 uses it several years already.

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Originally Posted by brentpresley

:stick:

That is a link to Core Duo not Core 2 Duo

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Hehehe!

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Originally Posted by brentpresley

:stick:

That is a link to Core Duo not Core 2 Duo

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Thank you! :D

Thank you that you did not break my expectations! I was sure that all fanboys will immediatelly stop thinking right after they read CORE DUE not c2d... :clap:

ok, enough laugh.
I repeat that link this way:
http://www.intel.com/technology/itj/...oved_cores.htm

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only scalar SSE operations are single uOps while the vector operations are typically 2-4 uOps.

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See? That's the term link it and it is the only purpose of link.

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Originally Posted by brentpresley

The SSE units were REWORKED in Core 2 vs. Core Duo.

That document specifically describes ONLY the enhancements in Yonah and doesn't cover Core 2 AT ALL (publication date is 3 MONTHS before C2D was released).

You analysis is invalid. :D :stick:

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Let me inform you that's why fanatism is so bad thihg.

I see I should bring my point explicitelly:

c2D has up to 6 nOps per cycle.
not SSE instructions per cycle!
uOp is NOT SSE instruction!

and thus the assertion

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Core 2 can issue a max of 6 SSE instructions per cycle, while the K10 can do 3.

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is wrong.

Additionally:

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If you just compare floating-point addition and multiplication, both Core and K8L can do four (packed) double-precision operations per cycle (2 x fadd + 2 x fmul) or eight (packed) single-precision operations per cycle (4 x fadd + 4 x fmul). The fact that there's FP/SSE MOV hardware on each of Core's three main issue ports will give the Intel part an edge in handling memory traffic, though.

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http://arstechnica.com/news.ars/post/20061011-7961.html


and for "in handling memory traffic" - AMD will balance it with other technic. So only time will show if it is 10% or whatever else...

ok, first, you admit that

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C2D has 3 128-bit SSE units

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that is it.

next,

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That STILL only gives a MAXIMUM throughput of 4 64-bit SSE instructions per cycle.

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wrong again...
you lost FSTORE

i did not get why you mentioned this "THIS HAS NOTHING TO DO WITH SSE INSTRUCTIONS ISSUED PER CYCLE".
Just in case - we never talked about it.


Back to "4 64-bit SSE instructions per cycle":
2xFMUL + 2xFADD + FSTORE (and + 2x 128 SSE loads)

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Originally Posted by brentpresley

You DO REALIZE you quoted the part where I was talking about K8L, right? So you are saying AMD is WRONG and they can't do 4 SSE 64-bit instructions per cycle?

It's really hard to talk out of both sides of your mouth, isn't it?

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Can you translate it to English pls.
While i repeat more clearly:

You are wrong with your sentence:

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Originally Posted by brentpresley

RUMORS on Rev H (K8L/K10):
Double SSE throughput on the 2 SSE units (i.e. expanded to 128-bits each, and each able to work on 2 64-bit SSE instructions per cycle). That STILL only gives a MAXIMUM throughput of 4 64-bit SSE instructions per cycle.

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So you can see - YOU are saing that, not me. You wrong.
Wanna laugh more?

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Originally Posted by SEA

Can you translate it to English pls.
While i repeat more clearly:

You are wrong with your sentence:

So you can see - YOU are saing that, not me. You wrong.
Wanna laugh more?

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umm K8L has 3 SSE/FP units
just like K7 and K8, the big difference however is that all 3 are 128bit

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Originally Posted by brentpresley

Because the integer and SSE units are COMPLETELY different parts of silicon that have NOTHING to do with each other.

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I'm glad you admit it.
I just wondered why you mentioned it at all? (you can leave it w/out answer btw, i see your point anyway)

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Originally Posted by nn_step

umm K8L has 3 SSE/FP units
just like K7 and K8, the big difference however is that all 3 are 128bit

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Did i say 4 or 2?

http://www.chip-architect.com/news/O...t_Core_Ill.jpg
though you are correct in that it is just 2 SSE, since it runs in FPMUL and FPADD

ah, you mean this:

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Originally Posted by SEA

2xFMUL + 2xFADD + FSTORE (and + 2x 128 SSE loads)

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Right and i hope everyone now can refresh his memory looking at picture :)

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Originally Posted by accord99

AM2's memory bandwidth is 12.8GB/s. If you plug in a Barcelona core into an AM2, that's all you get since there is physically only two channels connecting the memory to the socket.


Intel's current DDR2 memory controllers are already this way.

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And OCing raises tho's numbers through the roof. Nobody said there was a bandwidth wall limit. Your only talking about stock speeds. PPL have broken that wall long ago. Btw there is a difference between system bandwidth and memory bandwidth. And we all know everybody here OC's thats extreme.

http://www.amd.com/us-en/Processors/...E13042,00.html

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Originally Posted by brentpresley

I have been told benches will be forthcoming VERY soon (just what I have been told, remember, I don't have ES in hand, just contacts with them).

What's wrong Serge? PISSED I've got more info on Rev. H than you? Scooped your precious little thread here? :stick:

We all know this is your SECOND userid. Keep flamebating me, and we'll get that one banned as well. :fact:

Remember the LAST time you flamebated me claiming that 64-bit K8 performance at 2.8GHz was a FAST as C2D at 2.8GHz? :slap:

I made you look REALLY stupid with MULTIPLE benchmarks on that one. :fact: :slapass:

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The only one whos flaming is you. And frankly I didn't get banned. You'll see the 15th. Why would I be mad? Your silly and show you take this thread way too seriously like the kid you are. I don't have to respond to your BS any more. I don't take things personally over the net like you apperently do. :rolleyes: This is my friends account btw.

I'm surprised they haven't done anything about you with your framing yet. O_o

Oh you mean this?

http://s38.photobucket.com/albums/e1...urrent=ZX3.jpg
http://s38.photobucket.com/albums/e1...urrent=ZV4.jpg

http://s38.photobucket.com/albums/e1...&current=2.jpg

All it looks like to me I showed was K8 in 64-bit mode can beat conroe in math related calculations. ALU is what that is, so K8 has a advantage in loading things faster, doing operations and ALU related tasks faster that need a program like that such as games. But conroe has a advantage over K8 in 32-bit mode however. FPU's SSE from conroe has the advantage with multimedia and encoding here. And AMD has the bandwidth advantage here.

Conclusion Conroe is the best 32-bit chip ever made.
K8 is the best 64-bit chip ever made.

We are all the time talking about just SSE operations.
SSE LOAD is such one.

And one more time all together:
K10: FMUL + FADD + FSTORE (+ 2x SSE loads)
C2D: FADD + FMUL + FLOAD + FSTORE

the last one is from link you provided - http://www.xbitlabs.com/articles/cpu...preview_9.html

Youy sound pretty sure. ;)

What are those x87 operations you mentioned in?
FMUL?
FADD?
FSTORE?
2x SSE loads?

Or... i'm afraid to ask.. Have you gotten optimisation manual for barcelona?!!! :hm:

Ah, i see...

you mean they call it "FP execution units"
The ones what execute x87 / SSE (they both use same part ALU - sorry FPU).

Also - here is a perfect diagram a few posts above.

technically SSE was created for SIMD calculations but since most of the logic is the same they combine both SIMD and Floating point math. They could be separated but Intel and AMD see it as wasted transistors.

brentpresley
I have read :D

you 've got funny style - when you have nothing to say - you say common known things the way as if nobody but you knew it :)
Also could you please point more specific what have you corrected with your post? that FSTORE cannot process SSE stores?
Any link? Or your historical word is good enough? :)

Common, admit just once you were wrong! find time... :lol:

You even can find SSE fstore (=fmisk) in K8.
I CAN link http://www.xbitlabs.com/articles/cpu...amd-k8l_5.html:

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This is illogical since writes from the 128-bit SSE registers into memory are executed on the FMISC (FSTORE) unit

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oops... corrected link

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Originally Posted by brentpresley

NOT all FPUs are SSE enabled.


K8/K10 BOTH have 3 FPU units as pictured in NN_step's diagram. But only TWO of those are SSE capable.

x87 = FPU (floating point) calculations, but not all FPU opterations are SSE operations.

HISTORY LESSON:
Intel invented SSE (and subsequent variants) as a more efficient mechanism to do floating point calculations that the old x87 instructions were capable of. Over time these have been extended to aid repetitive calculations (multimedia comes to mind). However, for BACKWARDS COMPATIBILITY, x87 was always maintained in the CPUs.

AMD historically has made VERY powerful x87 FPUs, but not utilized SSE very much. Intel has approached things from the opposite perspective: they have made very good SSE units, and only maintained BASIC x87 compatibility in their FPUs. With more and more code being ported to run SSE, AMD is moving more to the Intel-approach to FPUs (i.e. better SSE performance).


PLEASE stop posting when you don't know what you are talking about. You really are showing your ignorance on the subject.

I don't have time to correct you on EVERY single point anymore.

Someone else step up to the plate and link this guy a basic description of x86 superscaler processors please.

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Your flaming. Please stop right now, you take things far too seriously. :rolleyes:

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Originally Posted by brentpresley

Someone else step up to the plate and link this guy a basic description of x86 superscaler processors please.

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But you're doing such a good job ;)

If the instruction fetch is a weakness in Conroe right now, it is likely that Intel will likely increase it to 32 bytes, like the K10.

Not sure how great a change this is, but it doesn't seem too radical.

**Edit** Just got this from the Xbitlabs article:

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By the way, Conroe processors fetch instructions in 16-byte blocks, just like K8 processors do, so they can decode the instruction stream at a rate of 4 instructions per clock only when the average instruction length is no longer than 4 bytes. Otherwise the decoder cannot process not only 4 but even 3 instructions per clock. To fight this in short loops, the Conroe has a special 64-byte internal buffer that caches loops up to 64 bytes long (four 16-byte blocks) and allows fetching data in such loops at a rate of 32 bytes per cycle. If a loop is longer than 4 blocks, it cannot be cached in this buffer.

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Apparently, the Intel engineers have found a clever work around for the instrution fetch limitation.

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Originally Posted by brentpresley

:ROTF:

The link you provided has this diagram:[]
CLEARLY showing 2 SSE units and FPMISC (non-SSE enabled FPU).

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The link I provided clearly states in text that FPMISC (=FSTORE) executes SSE STORES.

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Originally Posted by brentpresley

:stick: :stick: :stick:

STORE. It just STORES it for FUTURE use. No OPERATION is performed on it.

The instruction is not ISSUED (i.e. COMPLETED).


:stick: :stick: :stick:

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OK, I catch your sudden turn ;)

Now we don't count any SSE load/store/move operations since it turned out that they are not operations (aka No OPERATION is performed on it. :D )

Good.
Let's coun't so-called "OPERATIONS" :lol:
That is 4 SSE FP in C2D
That is 4 SSE FP in K10.

Done. So what was your point?

Mine initially was to correct this wrong sentence: "Core 2 can issue a max of 6 SSE instructions per cycle, while the K10 can do 3"

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Correct me if I am wrong, but that is how I read that.

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You are right this time.

SEA and Brent, cut out the flaming.

While not an official benchmark or anything, I found the comments of Dr. Vijay Pande from Stanford University to be interesting. He stated that the SSE128 units in the K10 are on par with Conroe's SSE performance. Perhaps they have tested an ES for folding. Combine that with the K10's projected vastly superior floating point performance, and the Barcelona should be a great chip.

I still haven't seen any projected numbers for integer performance though.

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Originally Posted by Scimitar

While not an official benchmark or anything, I found the comments of Dr. Vijay Pande from Stanford University to be interesting. He stated that the SSE128 units in the K10 are on par with Conroe's SSE performance. Perhaps they have tested an ES for folding. Combine that with the K10's projected vastly superior floating point performance, and the Barcelona should be a great chip.

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SSE is floating point and is necessary to extract maximum performance.

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Originally Posted by accord99

SSE is floating point and is necessary to extract maximum performance.

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ummm :banana::banana::banana::banana: NO..
Floating point is working with numbers that are arranged exactly like this
http://upload.wikimedia.org/wikipedi..._point.svg.png
and is Properly classified as SISD Or Single Instruction, Single Data Math.

SSE is SIMD or Single Instruction, Multiple Data, which uses a single instruction to perform the same work on many different Data fields at once.

This is the difference between SISD and SIMD
http://arstechnica.com/cpu/1q00/simd/figure6.gif


Floating point is used for scientific calculations when Fixed point math isn't acceptable (though these days the improvements in floating point have reduced that requirement) SSE is for Vector math and similar parallel instructions. Read about AltiVec if you want the most logical version of what exactly SIMD is

SSE1 is primarily about single-precision floating point, SSE2 is primarily about double-precision floating point. The way to extract maximum floating point capabilities from a modern x86 processor is to use SSE operations, plus x87 is deprecated in 64-bit Windows.

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Originally Posted by accord99

SSE1 is primarily about single-precision floating point, SSE2 is primarily about double-precision floating point. The way to extract maximum floating point capabilities from a modern x86 processor is to use SSE operations, plus x87 is deprecated in 64-bit Windows.

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SSE1 was merely the addition of the required logic to do the most basic Vector math; However SSE2 enables the programmer to perform SIMD math of virtually any type (from 8-bit integer to 64-bit float) entirely with the XMM vector-register file, without the need to touch the (legacy) MMX/FPU registers. SSE2 IS everything SSE should have been. And if you actually programmed something for once in your life that specifically makes usage of these pieces of the CPU, you would know they are VERY VERY different animals and your repeated speaking of them as the same is not only inaccurate but annoying.

That's nice, but irrelevant to the discussion at hand. And doesn't change the fact that maximizing floating point performance comes from using SSE.

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Originally Posted by accord99

That's nice. But that doesn't change the fact that maximizing floating point performance comes from using SSE.

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all math performance improves when you work with it, provided you are doing the same math to an entire set of data. Just because you think the Katmai (intel's SSE flagship) is the model for what SSE is.
It was a compromise, it implemented SSE using as little silicon as possible. To achieve this goal, Intel implemented the 128-bit architecture by double-cycling the existing 64-bit data paths and by merging the SIMD multiplier unit with the x87 scalar FPU multiplier into a single unit.

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Originally Posted by accord99

That's nice. But that doesn't change the fact that maximizing floating point performance comes from using SSE.

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That would depend on the specific sequence of instructions, whether SIMD operations would be possible, in the branch conditions, in the dependency within the instruction stream. There is no single magic formula in maximizing performance of software in general; those that can utilize a high percentage of SIMD ops usually belong to specific types of applications.

Quote:

---

Originally Posted by Carfax

But you're doing such a good job ;)

If the instruction fetch is a weakness in Conroe right now, it is likely that Intel will likely increase it to 32 bytes, like the K10.

Not sure how great a change this is, but it doesn't seem too radical.

**Edit** Just got this from the Xbitlabs article:



Apparently, the Intel engineers have found a clever work around for the instrution fetch limitation.

---

I am not sure Xbit is accurate on this.... I think they are assuming a 4 instructuction fetch at an average of 4 bytes instruction length so to make 16... but Arstechinica published a rouge presentation that shows a 6 instruction written and 5 fetched... using the 4 byte average length, this would come to 20 bytes.... but I am not sure of the accuracy of the report.
http://arstechnica.com/news.ars/post/20060626-7135.html

Puuhh....what a bunch of random stuff taken from thin air. Lets just keep the focus here....

C2D got 3 128bit SSE units, K8L got 2 128Bit SSE units (Even AMD themselves says 4 64Bit SSE instructions per cycle max...so unless AMD is full of lies.). Also I wodner why this is such a big deal for the fanboys. SSE is only a minor thing. Look at games..C2D at same FSB/Speed is what..10-20% faster than CD. And thats with 6x SSE performance, macro fusion, bigger and better cache etc etc etc etc.

On another sidenote. SSE replaces x87 in 64Bit Windows. So in time x87 will be gone with time...long time. :P

http://www.anandtech.com/showdoc.aspx?i=2768&p=3

Quote:

---

Originally Posted by Shintai

Also I wodner why this is such a big deal for the fanboys. SSE is only a minor thing. Look at games..C2D at same FSB/Speed is what..10-20% faster than CD. And thats with 6x SSE performance, macro fusion, bigger and better cache etc etc etc etc.

---

C2D doesn't have 6x the SSE performance as CD. It has 6x the theoretical performance. Thats an important distinction.

Ofcourse, in the real world, you rarely, if ever get to anything close to theoretical performance.

Still, I think you're not giving C2D enough credit. Here are some tests which have SSE optimizations between C2D and CD:

I'll just link the benchmarks instead as the pics weren't showing up

In both tests, C2D is 25 to 30% faster than CD, and while these apps contain significant SSE optimizations, they are by no means the most heavily optimized SSE apps around.

The most heavily optimized SSE app I've ever seen is Lightwave.. I remember when it first became SSE2 optimized, and the P4 just :banana::banana::banana::banana::banana: slapped the K7 at the time. Then, when the K8 came out, AMD caught up as it had SSE2 capability.

But now that C2D is out, it just rapes the K8:

http://common.ziffdavisinternet.com/...=133055,00.gif

The X6800 is 122% faster than the K8 in this benchmark..

So it just goes to show, that SSE does matter, and can significantly speed up an application's performance if tuned correctly.

Sadly though, developers rarely ever put the effort in to really get good gains from SSEx.

Also, SSE4 will help even more potent from what I hear, and is expected to provide healthy double digit percentage gains on top of what SSE2 can currently do.

Your bench is kinda worthless if it doesnt compare something thats already equal. It can just aswell be cache, macro fusion, speculative fetch etc. We still need a CD in the test as its the cloest relative to C2D. And we need it in a broad view of it. And you do know other rendering SW thats also SSE thats afster on AMD. One bench cant be used for conclusions, even tho I know what your hopes are with it. (But its a dream)

Just take 3Dmax7 and its a whole lot different (Or Cinebench).
http://www.anandtech.com/cpuchipsets...px?i=2795&p=11

Now what you should have done if you wanted to make any conclusion. Is to take an equal FSB Core and Core 2 like in this mobile view:
http://www.anandtech.com/cpuchipsets...spx?i=2808&p=1

So...your SSE conclusion is...wrong.

And please do note:
http://www.anandtech.com/cpuchipsets...spx?i=2808&p=4

How much difference is needed just for the performance delta between the 2.

Quote:

---

Originally Posted by Shintai

Your bench is kinda worthless if it doesnt compare something thats already equal. It can just aswell be cache, macro fusion, speculative fetch etc. We still need a CD in the test as its the cloest relative to C2D. And we need it in a broad view of it. And you do know other rendering SW thats also SSE thats afster on AMD. One bench cant be used for conclusions, even tho I know what your hopes are with it.

Just take 3Dmax7 and its a whole lot different (Or Cinebench).
http://www.anandtech.com/cpuchipsets...px?i=2795&p=11

---

What? Did you even look at the benchmarks?

I provided 2 benchmarks which had a Core 2 Duo and a Core Duo, at very similar clockspeeds. Those were the encoding tests.

The rendering test didn't have a Core Duo, but it did have a K8 and a P4.

Also, since the C2D came out, there is no rendering software that I know of which performs faster on the K8.

When the K10 debuts, this may change, but as for now, C2D rules the roost in rendering.

But my point with the Lightwave bench was to show you that SSEn optimizations when done correctly, can give some hefty performance increases.

Quote:

---

Originally Posted by Shintai

Now what you should have done if you wanted to make any conclusion. Is to take an equal FSB Core and Core 2 like in this mobile view:
http://www.anandtech.com/cpuchipsets...spx?i=2808&p=1

So...your SSE conclusion is...wrong.

And please do note:
http://www.anandtech.com/cpuchipsets...spx?i=2808&p=4

How much difference is needed just for the performance delta between the 2.

---

Um, I explain this earlier when I replied to one of your posts somewhere at the top of the page.

The reason why the performance delta between C2D and Core Duo is smaller in the Anandtech review is because the C2D is bandwidth starved by running at such a low FSB.

Granted, the Core Duo is also bandwidth starved, but the Core 2 Duo is even more so, as it has far more execution resources to feed.

The two encoding benches I used as examples, had the Core Duo running on a desktop mainboard, so the FSB could be cranked up.

Therefore, the performance delta between the Core Duo an Core 2 Duo in that review was much higher than the Anandtech review.

Quote:

---

Originally Posted by Carfax

What? Did you even look at the benchmarks?

I provided 2 benchmarks which had a Core 2 Duo and a Core Duo, at very similar clockspeeds. Those were the encoding tests.

The rendering test didn't have a Core Duo, but it did have a K8 and a P4.

Also, since the C2D came out, there is no rendering software that I know of which performs faster on the K8.

When the K10 debuts, this may change, but as for now, C2D rules the roost in rendering.

But my point with the Lightwave bench was to show you that SSEn optimizations when done correctly, can give some hefty performance increases.

---

No..you provided a benchmark with a 1066FSB C2D vs a 667FSB CD. As I said, compare something equal if you want to bench. I provided you with benchmark of a CD and C2D with the SAME FSB! And we all (cept you maybe) that encoding is heavily memory bandwidth dependent.

Also your benchmark site got a 945G chipset vs a 975X in the comparision.

And even then...I guess you wanted to skip the rendering part of the review you added aswell?
http://www.behardware.com/articles/6...-duo-test.html

Not really much difference is there?

Quote:

---

Originally Posted by brentpresley

DUH. :stick:

With EACH able to perform on 2 x 64-bit operations each.

---

Like described in AMD's patent no. 6,944,744?

Well, I didn't read so far, that C2D could issue 2x 64bit operations to each of the FMUL/FADD ports (4 µOps to 2 ports in one cycle).

It's also important to note, that SSE loads/stores and mem operands are handled by separate µOps. There K10 is behind, because it only can handle up to
1 FMUL
1 FADD
1 FMOV (in FMISC, since FMUL/FADD are already in use)
2 load operations (as memory operands)
per cycle.
It's even possible to keep that level by decoding only 3 SSE ops per cycle. However, this is a theoretical maximum. Most operations seen in real world don't care about such maxima (because it's difficult to exploit them all the time). You'll often see MULPD/ADDPD mixes with some SHUFPDs and MOVAPDs and mem operands.

What was the thread title again???:confused:

"The Ultimate Core2Duo Vs Core DUo Thread 2007 & beyond!!!" ???

Of course not.Sad.:slapass:

K8L will rock , you only need to have a little faith. ;)

Quote:

---

Originally Posted by brentpresley

Fanboy's have plenty of faith.

What we are lacking are benchmarks.

---

And your flaming again:mad:

Please keep on topic now
This is about K10 only

Brent ,dude,you guys are even not discussing/speculating the K10 ,you are talking about the Core Duo(as Yonah...) man!THAT IS SAD.Period!

Quote:

---

Originally Posted by brentpresley

My posts had C2D (NOT Yonah) comparing K8L/K10.

Since they will be DIRECT competitors, that is a VERY FAIR comparison.

Your just pissy b/c all there is to talk about is speculation.

---

I've read through this thread and I'm eager as the next guy to see what the future holds, but what in the world is the point of arguing about something we are speculating about. Lets just wait and see. Calm down people. Brentpresley, just ignore those who flame because they don't like a point you've made. Come on people.

Ok, how about this, this thread is about AMD. Not about comparing to Intel. Brent, call someone a fanboy and you will be taking some time off.

Keep the thread on topic and stay the he** out if you have nothing worth saying.

K?
K.

IFMU

These policies are absurd..

How can you discuss AMD without discussing their principal competitor Intel?

They are two sides of a coin, and the C2D is the only barometer we have for estimating the performance of the K10, therefore any discussion on the C2D as it relates to the K10, is valid.

I posted the C2D and the K8 benchmarks, because I wanted to demonstrate the value of a good SSE2 implementation (which is important to AMD), which Shintai was dismissing..

Quote:

---

Originally Posted by Carfax

These policies are absurd..

How can you discuss AMD without discussing their principal competitor Intel?

---

Well no one is forcing you to stay here.
I am sick of people who hate AMD/Intel going into the others section and doing nothing but bashing those who like the section THEY ARE IN.
If you dont like one brand, go to the other section and stay there.
By the gawds is it so hard to have a discussion about something without someone having to call you a fanboy because you like one over another?
If you want to discuss AMD vs Intel or AIT vs nVidia? then do in in the General Hardware areas, not in the areas that are dedicated to them specificly.
Is that hard to comprehend for anyone?
If I think all cars suck I am not going to go into the Car/Trucks section just to tell everyone they are fanboys.

It is the way it is, if you dont like it no one is forcing anyone to be here.
This is not a democracy.

IFMU

P.S. Yes you can report this post to other staff if you feel I have attacked you in some way.

Otherwise
Accept it
Acknowledge it
Move on.

does any on have any idea how much will these k8l chips cost, when they come out?
and does any one know the date when they WILL come out?

Well according to Amd they come in q2 2007 and hkepc had a article stating that K10 Opterons come from 1,9-2.5 ghz in q2 2007 .
I have posted the links in this thread. Im too lazy to search true 26 pages with mostly arguing now, sorry . Perhaps i relink them later.

We will probably see Opterons Barecelona (socket 1207 2p 4x2=8cores) and
Budapest (Am2 Opterons 1000series). But they will probably be few in the channel:(. As for prices . I would guess cheapest for 400$.




http://www.xtremesystems.org/forums/...6&d=1168793639

Ok found one :)
I see if i can link the others later:)

ok thanks for the info gues, so mid 07 thats too long i want one now :D

Quote:

---

Originally Posted by IFMU

Well no one is forcing you to stay here.
I am sick of people who hate AMD/Intel going into the others section and doing nothing but bashing those who like the section THEY ARE IN.
If you dont like one brand, go to the other section and stay there.
By the gawds is it so hard to have a discussion about something without someone having to call you a fanboy because you like one over another?
If you want to discuss AMD vs Intel or AIT vs nVidia? then do in in the General Hardware areas, not in the areas that are dedicated to them specificly.
Is that hard to comprehend for anyone?
If I think all cars suck I am not going to go into the Car/Trucks section just to tell everyone they are fanboys.

It is the way it is, if you dont like it no one is forcing anyone to be here.
This is not a democracy.

IFMU

P.S. Yes you can report this post to other staff if you feel I have attacked you in some way.

Otherwise
Accept it
Acknowledge it
Move on.

---

thanks for stepping into this thread and placing a logical order into the manner upon which people should be posting in this thread and most importantly in this particular part of the forum.

its difficult to understand how some clearly inteligent people are unable to understand the concept of the forums title; AMD. While discussion is required between both competitors cpus this comparison, analysis and disection should be conducted in the correct part of the forums. This is not the place to do it.

The general hardware section would welcome the traffic ;) Please peeps, take it to the correct section and leave the 'fanboys' to discuss the cpus they like without the need to defend this.

im thankful to the mods here at XS, they keep things from really boiling over, nipping it in the bud. Sometimes it looks like they aint around but when required their presence can be felt.

:clap:



mong

Amen to that IFMU...I want to read information, not fight flames.

I don't know anything about K8L, but I'd like to know what type of memory K8L mobos will support. I want to invest in a K8L system later, so I'd like to keep my eye open for any deals. Or do you recommend waiting because better memory tech for K8L systems will be available sometime next year?

K8L will support DDR2 and DDR3. I would wait until 2GB modules become a little more mainstream, if you ask me.

Ah good advice. Thanks :) Yeah I saw those 2x1g Corsairs being sold for over $650. Who ever spends that kind of money on two sticks of ram, I have a bridge for sale.

Edit:
Wait a minute... did you just say DDR3? Like the memory they put in vcards? Whats different about it? I must know more about this "DDR3"!!

Quote:

---

Originally Posted by Judaeus Apella

Wait a minute... did you just say DDR3? Like the memory they put in vcards? Whats different about it? I must know more about this "DDR3"!!

---

There's a DDR3 Guru around here somewhere, but he's pretty shy and doesn't post much.

Quote:

---

Originally Posted by Judaeus Apella

Ah good advice. Thanks :) Yeah I saw those 2x1g Corsairs being sold for over $650. Who ever spends that kind of money on two sticks of ram, I have a bridge for sale.

Edit:
Wait a minute... did you just say DDR3? Like the memory they put in vcards? Whats different about it? I must know more about this "DDR3"!!

---

Do not ever confuse DDR3 with GDDR3, because they are very different animals

DDR3 is essentially DDR2 with a process shrink. Which means:

-lower voltage
-higher clocks
-higher capacity

Quote:

---

Originally Posted by ether.real

DDR3 is essentially DDR2 with a process shrink. Which means:

-lower voltage
-higher clocks
-higher capacity

---

NO and BAD :slap:
DDR3 supports any new features such as:
1)Introduction of asynchronous RESET pin
2)Support of system level flight time compensation
3)On-DIMM Mirror friendly DRAM ballout
4)Introduction of CWL (CAS Write Latency) per speed bin
5)On-die IO calibration engine
6)READ and WRITE calibration
7)Fly-by command/address/control bus with On-DIMM termination
8)High precision calibration resistors

Which means lower power, Lower latency, more bandwidth and Higher capacity.

Ah, thanks step and ether.

Quote:

---

Originally Posted by nn_step

Do not ever confuse DDR3 with GDDR3, because they are very different animals

---

Sh*t... You don't think I angered the gods of overclocking do you? I hope I don't need a sacrifice for my Delta fan... :(

http://pc.watch.impress.co.jp/docs/2...kaigai_01l.gif

http://pc.watch.impress.co.jp/docs/2...kaigai_06l.gif

http://pc.watch.impress.co.jp/docs/2...kaigai_07l.gif

http://64.233.179.104/translate_c?hl...%3Den%26sa%3DG

Wow, its just amazing to me to see something that small, knowing how powerful it is.

read http://www.chilehardware.com/foro/cp...ight=barcelona
what do they speak about?

Quote:

---

Originally Posted by MAS

read http://www.chilehardware.com/foro/cp...ight=barcelona
what do they speak about?

---

Well, he said he have a cpu that CPU-Z can't detect at all in the first post, later he said it wasn't Intel... so basicaly he is saying he got a K10 in hands.

if you look at the pic , it does say unknown amd cpu

here is the english version
http://64.233.179.104/translate_c?hl...ht%3Dbarcelona

You gonna need AM3 for DDR3. AM2+ will only do DDR2.

http://www.hkepc.com/bbs/itnews.php?...me=0&endtime=0

Quote:

---

Originally Posted by nn_step

NO and BAD :slap:
DDR3 supports any new features such as:
1)Introduction of asynchronous RESET pin
2)Support of system level flight time compensation
3)On-DIMM Mirror friendly DRAM ballout
4)Introduction of CWL (CAS Write Latency) per speed bin
5)On-die IO calibration engine
6)READ and WRITE calibration
7)Fly-by command/address/control bus with On-DIMM termination
8)High precision calibration resistors

Which means lower power, Lower latency, more bandwidth and Higher capacity.

---

I LOOOOVE those "lower' parts

-tam2-

Quote:

---

Originally Posted by DoubleZero

Well, he said he have a cpu that CPU-Z can't detect at all in the first post, later he said it wasn't Intel... so basicaly he is saying he got a K10 in hands.

---

he also says he signed an NDA.I cant fathom how chile rates among the ES recipients And me;joe america does not :peace:

Quote:

---

Originally Posted by brentpresley

http://www.xbitlabs.com/news/cpu/dis...203151532.html

2 Years 5 months is not 3 years. ;)

---

seemed alot longer than that to me lol. i'm not an old school clocker though, when i had a pentium mmx you guys were on athlon xp's with barton cores 'n such. and when i came on this board i had a compaq computer lol. but i remember some ppl said clock for clock pIII was quicker than pIV that made me lol.

Quote:

---

Originally Posted by brentpresley

There are some MAJOR motherboard manufacturers down there. ;)

---

:surf: likely excuse.:D

Quote:

---

Originally Posted by verndewd

he also says he signed an NDA.I cant fathom how chile rates among the ES recipients And me;joe america does not :peace:

---

Quote:

---

Hay muchas cosas que no podemos mostrar primero en ChileHardware porque quienes nos las pasan nos hacen firmar contratos de confidencialidad hasta ciertas fechas (NDA).

---

He said that there are many things that they can't show first in ChileHardware because the ones that provide the stuff make them sign UP a NDA until a certain date.

So I guess he's going to reveal what they got in a while.

Also in the next page he said that the screenshot was edited because some info did show up.

Quote:

---

Originally Posted by verndewd

:surf: likely excuse.:D

---

location is far less important than who you know

Quote:

---

Originally Posted by IFMU

Well no one is forcing you to stay here.

It is the way it is, if you dont like it no one is forcing anyone to be here.
This is not a democracy.

IFMU

P.S. Yes you can report this post to other staff if you feel I have attacked you in some way.

Otherwise
Accept it
Acknowledge it
Move on.

---

God bless you IFMU

I for one will not complain about this post.

I believe you should be given a medal!

Isn't it funny how all these know all trolls can't spell.
One wonders where they got their education.
Intel marketing manuals I think.

I hope these new chips are out soon, my poor old S939 170 is starting to feel the pinch.

What do you guys think will be the price of the cheapest Dual core K10 and Quad core K10??

Quote:

---

Originally Posted by Kingcarcas

What do you guys think will be the price of the cheapest Dual core K10 and Quad core K10??

---

Initially it might be a bit because AMD will release QuadCore variants at first which by definition are expensive (for now). As someone before was guessing I think between $400 and $1000 per chip.
Before end of 2007 AMD will start selling DualCore variant of K10 so it will automatically fit into $200-$600 price range.

That is my personal opinion... :)

Quote:

---

Originally Posted by Kingcarcas

What do you guys think will be the price of the cheapest Dual core K10 and Quad core K10??

---

look at X2 pricing and you'll get a very good idea

You really think it will be like X2 pricing? They are almost giving them away right now.

AMD commanded a lot of money for X2 before C2D, and at that time X2 was an all around better performer(performance, heat, power, etc) then the Intel dual core offering, and AMD was not shy about charging us, which I think was very wise on their part.

If the new chips perform this 10-40% everyone is rumoring about, then I would say look at the C2D pricing, not the X2. I'm guessing it will be very near it's Intel counterpart. Just IMO.

EDIT: Of course I hope you are correct! LOL.

Quote:

---

Originally Posted by aicjofs

You really think it will be like X2 pricing? They are almost giving them away right now.

AMD commanded a lot of money for X2 before C2D, and at that time X2 was an all around better performer(performance, heat, power, etc) then the Intel dual core offering, and AMD was not shy about charging us, which I think was very wise on their part.

If the new chips perform this 10-40% everyone is rumoring about, then I would say look at the C2D pricing, not the X2. I'm guessing it will be very near it's Intel counterpart. Just IMO.

EDIT: Of course I hope you are correct! LOL.

---

you do realize that the Price when X2 came out, it was alot higher than it is now :rolleyes:

Quote:

---

Originally Posted by nn_step

you do realize that the Price when X2 came out, it was alot higher than it is now :rolleyes:

---

Yeah original X2 pricing I agree with.

When I bought my opty 170 4800's were $990 in Australia, roughly $600usd.

The 170 was $650aud 12 months ago.