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Kadaj,Quote:
Originally Posted by Kadaj
Sorry to be lame.. what does "VT" samples mean? I have an 955 mobo, and trying to AVOID going to 975 :) These presslers looks promising, so if you can let me know what VT means.. that would be great. From waht I read, only the Pressler EE are suppose to be 975 exclusive, right?
SAD
Intel VT Click linkQuote:
Originally Posted by SuAsDu
wow!
enjoy man
and come back with results :D
How did he get one??? Jeeeeeeeeezzz, I want one YESTERDAY !!!!!!!!!!!!!!!!!!!
:confused: Works there? Knows/bought from someone who works there? Reviews cpus for Intel? Bought off of Ebay :D ?Quote:
Originally Posted by Think
Support HT??? is this HT hyper threading? then it has 4 logical units OMG!!!
i have a question does NF4 SLI Intel Edition support this CPU? since this board is faster than the 955x due to the test
i'm from china, and there truly are someone sells 950es, for around 500$ each. overclocked to 4.9Gx2
Asus P5WD2 pwns any Intel NF4 sli, you dont want the NF4 chipset for intel... :nono:Quote:
Originally Posted by AudiS4
Quote:
Originally Posted by Welz
what's pwns stands for? sorry for that, i am a foriegner.
but, why not? i heard that 955x need specific driver to support SLI is that true? then when we wanna upgrade the driver there will be a lot of problem...
well the test was from some chinese website, but looks NF4 SLI IE beat 955x and not far from 975, besides, it's cheap :p:
Only the Pentium D 955 Xtreme Edition supports HT. :)Quote:
Originally Posted by AudiS4
Pwns means own. As in 955X owning all Intel NF4 sli :stick:
I see~ that board is not cheap though,well anyways who will buy 950 or 955xe will not stint on the mainboard....Quote:
Originally Posted by Salvador
4mb L2 cache is nice.
but the combined L1 cache is still at 28k, same as the previous P4 gen processors. Would be a huge jump in performance if they double the amount. L1 caches are critical.. I wonder what keeps Intel from doing this. There's got to be reasons.
I'm ancious to see how it will perform in 3D games... hoping to see a large boost
the L1 in netburst chips is mainly there to draw information from the L2 (think of it as a high bandwidth bridge). their cache is also inclusive, so the L1 is copied into the L2. originally the L1 and 2 were much lower latency, that changed with prescott and prescott 2mQuote:
Originally Posted by IamAnoobieCheez
and the L1 cache size is 16KB per core, so its actually 32KB (unless youre referring to the trace cache, but thats not measured in KB's but KμOps. the trace cache size wasnt increased because intel thought performance increase was negligable IIRC)
the 900series chips will perform the same as 600 series chips in games, so expect an approximate 3% increase in gaming performace at the same clocks as an 800 series chip
considering the cache size increase the performance increase is pretty small. There really was only a limited number of applications that benefited, it was more of a marketing move really. However you look at it, the extra cache increases the size of the chip by 40%, for at best a 10% improvement. Wouldn't it have been better for intel to keep the smaller cache, so they can make more cpu's, sell them cheaper, and have us clock them higher due to the lower cache. Plus the l2 cache would still be the lower latency cache used in the 5 series. The 6 series was a nice improvement (mainly in terms of features and lower thermal dissapation through speed step) over the 5 series, but the decision to double the cache seems a bit bizarre.
However the 65nm process looks very nice, so these chips should clock great. Its just a shame that intel dont keep the netburst architecture alive in some form until the 'fixed' 45nm process - would love to see how they would perform at the designs intended clockspeeds.
the problem with the way they doubled the L2 is that they increased the L2 latency even further than it was on the 5xx series chips (so in some cases, it can hurt the performance). it tends to help scaling though...your right about the marketing angle. bigger #'s sellQuote:
Originally Posted by onewingedangel
the 6xx series also saw HT improvements as well, and the extra L2 is supposed to partialy serve as a bigger buffer when the HT core is processing load intensive applications, so as to not drain from the main core even more.
not lame at all, VT= vanderpool technology. a new real-time virutal partition hardware level technology that windows Vista will be incorporating.Quote:
Sorry to be lame.. what does "VT" samples mean?
netburst has far out-lived its estimated life-span, frankly I'm suprised Intel is even going through 65nm presler and cedar mill. It's likely just to embed the new number scheme as much as possible so that when the sub "3.8ghz" (or if K8 ends up faster clocked) conroe and memron's arrive, no one will care anylonger on clock speed, only if it's a 8xx or 9xx.. ectQuote:
However the 65nm process looks very nice, so these chips should clock great. Its just a shame that intel dont keep the netburst architecture alive in some form until the 'fixed' 45nm process
Whilst the netburst design ran into a brick wall in terms of scaling due to leakage issues, with the brick wall removed the processor architecture may yet prove extremely useful. Especially in situations where clock speed matters, such as performing many simple operations such as video encoding. For such a task, adding cache wont really help, and adding cores will only help if the software can fully support it. However, having many netburst cores clocked highly may outperform a core with a higher ipc in such an operation.Quote:
Originally Posted by Kadaj
By the time of the 45nm process though we may have cpu's with mixed execution units, and additional specialised processing engines, so why not utilise both design philiosophies if they both work well for a target task - have a core with both netburst, and the next generation high ipc design.
I didn't explain my part very clearly.. what I meant was that the size of the combined L1 cache(16kb data + 12kμOps) has not been increased with this Presley core. yes... I'm aware of the L1 data being passed on(copied) to the L2 for processing but why not Intel increase the L1 to 32KB data(64KB effective double core)... A long ago I've read that the importance of the L1 is absolutely critical.. Instead of keep doubling the L2 and loosening up the latency so much why didn't they increase/ or tweak up the L1 department... I always felt let down about this... there's got to be reasons for this :slapass:Quote:
Originally Posted by AkXb70
This will likely to bump up the gaming performance by 10%(figurative speech)..
im not entirely sure why, but i think it has to do with the trace cache and how it operates. i may be completely wrong here, but i think the trace cache relies on a small L1 to function
Hey hookie, check your pm or emails.
I have one of these on the way - do you think it will work in my NF4 board?
I am thinking of swapping to 975x anyway (the p5wgd2 looks good) but I am well annoyed that I may have to get rid of my SLI GTs if I go that route. I really hope Nvidia decide to support 975 as they will lose a few customers otherwise.
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Originally Posted by markodude
Where did you get it from?
You mean from "the dark side" :DQuote:
Originally Posted by FragTek
I got it from " a friend" - well not quite yet, he is bringing me it for Christmas - he has it in his hands now but is on the other side of the planet!
Looks like from th vrzone review the P5WDG2-WS is the board to go for - and they have SLI working too :)
Does it work on 945 motherboard? particularly, P5LD2?
I believe the regular 9 series should work on all 945 and 955 boards after a bios flash. the 955xe needs the 975 chipset though.