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well I'd like too see more since intel can do 20% from Nehalem to Sandybridge.Quote:
Originally Posted by FlanK3r
Also see that they're behind with phenom II at 15% and 20% more that's 35% would only match Sandybridge.
this is the only numbers we have with no clock speed mentioned EVER.Quote:
Originally Posted by JF-AMD
so in the same time that 100% work was done on 12 cores this 16 core dose 150% work done in the same time.
I believe AMD said that there was some problem with Llano and production and then a lot of people assumed the worst, that BD would be delayed (some were gloating a fair bit). Llano was first aimed at Q4 2010. I believe it is in the slides from analyst day in November.Quote:
Originally Posted by Mechanical Man
Demon: In single operatiopn dont know, but in multithread is very likely better performance (SB 4c+4t vs Zambezi 4c+4 "lower" cores)
20% will be a very positive increase, perhaps on benches where HT already shines, yes you might en up with 20% more, but otherwise, no.Quote:
Originally Posted by demonkevy666
with such an aggressive BD cpu clock speed and turbo I think we are in for some surprises.....
I've never seen Q4 2010 as an official launch interval for Llano.Quote:
Originally Posted by marten_larsson
http://prohardver.hu/dl/upc/2009-11/13063_deskroad.png
There are no "lower" cores in Zambezi,all cores are equal. Also,doing integer intensive work across all the 8 cores(or 4 cores in 2 module model),Zambezi will feature the same improved Turbo Core which will allow it to boost clocks across all the cores.With Interlagos we have 16 cores @ 115W and 500MHz boost,while with Zambezi we have 8 cores @ 125W and ????Mhz boost.Quote:
Originally Posted by FlanK3r
I have a faint memory of seeing a slide of which the Brazos launch was put ahead of schedule and Llano being behind. Also, from this summer (July ~7th) Dirk confirmed that there was a delay but I'm not 100% sure if that site was correct. I'll try to find it again.Quote:
Originally Posted by Oliverda
Edit:
Found it:
Source:Quote:
he news isn't all bad. Even as he informed the press that Llano could ship as much as six months behind schedule, Meyer made a point of noting that the company's next-generation Ontario processor will ship for revenue beginning in Q4 of 2010. Up until now, Ontario wasn't expected until later in 2011; AMD has neatly swapped the positions of the two products.
http://hothardware.com/News/AMD-Flip...nding-Forward/
infromal: yes, but u know how i thougt about it :)...About turbo, for desktop for all cores will simillary (500 MHz boost), for single or dual jump more MHz turbo.
I don't know squat about Llano other than what my boss said. There was a quote in the press about a month ago saying that we would launch it "in the summer."Quote:
Originally Posted by Mechanical Man
I guess Phenom 2 will have to cover AMD's dual core segments till Summer then. Maybe that will mean quad/hexa core phenom 2s for the price of dual core Sandy Bridges? Not a bad proposal I'd say.
Llano will be ok as long as it doesn't take much longer than July, Intel needs SB more than AMD needs Llano at this point since the former doesn't produce discrete graphics chips. Bulldozer is where the game is at for AMD so it should be highest priority for sure.
When is bulldozer coming out vs. when is sandybridge due out?Quote:
Originally Posted by Dimitriman
Right now both teams aren't impressing me. I don't want to get a i7 cause the board are crazy expensive but don't really seem to offer anything I can't get on a $50 cheaper P55. AMD is way more price efficient but a X6 isn't blowing any quads out of the water in gaming.
you must be looking at regular reviews where they dont customize the system very much. you can easily modify turbo to work in your favor to use 4 cores at like 4.2+ghz while your overall clocks are around 4ghz to keep your heatsink from making to much noise. an x6 should easily give you 50% more in multi threaded since your x6 clocks can match any deneb x4, then your max speed for a few cores can be higher to get you that 10% more out of it.Quote:
Originally Posted by Glow9
also cpu limitations in games might be easily corrected by changing a few settings so its back to gpu bound. since your weighing the pros and cons, make a choice for your price range
I don't think AMD will use Deneb to combat with Sandybridge 2C but Propus.Quote:
Originally Posted by Dimitriman
The ~30% die size difference is crucial in a price war.
Great news!
New BD information found by Dresdenboy:
http://citavia.blog.de/
Quote:
4.5 Design Solutions for the Bulldozer 32nm SOI 2-Core Processor Module in an 8-Core CPU
T. Fischer, S. Arekapudi, E. Busta, C. Dietz, M. Golden, S. Hilker, A. Horiuchi, K. A. Hurd, D. Johnson, H. McIntyre, S. Naffziger, J. Vinh, J. White, K. Wilcox, AMD
The Bulldozer 2-core CPU module contains 213M transistors in an 11-metal layer 32nm high-k metalgate SOI CMOS process and is designed to operate from 0.8 to 1.3V. This micro-architecture improves performance and frequency while reducing area and power over a previous AMD x86-64 CPU in the same process. The design reduces the number of gates/cycle relative to prior designs, achieving 3.5GHz+ operation in an area (including 2MB L2 cache) of 30.9mm2.
4.6 40-Entry Unified Out-of-Order Scheduler and Integer Execution Unit for the AMD Bulldozer x86-64 Core
M. Golden, S. Arekapudi, J. Vinh, AMD
A 40-instruction out-of-order scheduler issues four operations per cycle and supports single-cycle operation wakeup. The integer execution unit supports single-cycle bypass between four functional units. Critical paths are implemented without exotic circuit techniques or heavy reliance on full-custom design. Architectural choices minimize power consumption.
Direct link to pdf.Quote:
14.3 An 8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing
D. Weiss, M. Dreesen, M. Ciraula, C. Henrion, C. Helt, R. Freese, T. Miles, A. Karegar, R. Schreiber, B. Schneller, J. Wuu, AMD
An 8MB level 3 cache, composed of 4 independent 2MB subcaches, is built on a 32nm SOI process. It features column-select aliasing to improve area efficiency, supply gating and floating bitlines to reduce leakage power, and centralized redundant row and column blocks to improve yield and testability. The cache operates above 2.4GHz at 1.1V.
For comparison,here's Llano core specs:
http://pc.watch.impress.co.jp/img/pc...tml/5.jpg.html
Voltage:0.8-1.3V (same as BD design)
Core:~9.69mm^2 (35M transistors)
L2+Power Gate Ring: ~8mm^2
Total Core+Power Gate Ring+L2 size :~17.7mm^2 (110M transistors)
Clock target: >3Ghz ( 3.5Ghz for BD,so BD has a slight upper hand here too)
BD 2-Core module takes 30.9mm^2 Vs 2x17.7mm^2=35.4mm^2,so similar trans. budget in a smaller die area.On top of the more efficient die area usage we have more performance in 1 module Vs 2 Llano cores.
whats the point of having 4 independent L3s? is the yield on those things different so its not like if a little is bad the whole thing goes too?
I think it may have the similar design approach as SB LLC:Quote:
Originally Posted by Manicdan
SB uses ring bus and I have no idea if anything similar will be in BD uncore. What is known is a higher clock rate on the L3,2.4Ghz+.Quote:
The L3 cache is divided into slices, one associated with each core although each core can address the entire cache. Each slice gets its own stop and each slice has a full cache pipeline. In Westmere there was a single cache pipeline and queue that all cores forwarded requests to, in Sandy Bridge it’s distributed per cache slice.
so basically perf to its own L3 will be slightly higher, while still having access to the other slices?
So absolutely no new information about Z-RAM I take it.Quote:
Originally Posted by JF-AMD
Quote:
Originally Posted by informal
45nm Thuban: 904M - 346 mm˛
32nm Gulftown: 1170M - 248 mm˛
32nm BD module: 213M - 30.9 mm˛
BTW:
http://prohardver.hu/dl/upc/2010-04/...westmere_s.jpg
Z-RAM is dead.Quote:
Originally Posted by nn_step
"Pellerin also said that GlobalFoundries is no longer pursuing the one-transistor ZRAM developed by Innovative Silicon Inc. (ISI, Lausanne, Switzerland), a capacitor-less design based on SOI substrates. Instead, GlobalFoundries is working on a thyristor-based memory with T-RAM Semiconductor Inc. (Milpitas, Calif.). GlobalFoundries and T-RAM announced in mid-May that GlobalFoundries would co-develop 32 and 22 nm versions of the T-RAM, which is based on SOI technology, for low-power cache applications."
source
so...thats mean, 2.4 GHz+ uncore????
1.3V is the same as operating Thubans at default clocks.
@Llano transistors:
Does someone have numbers for the transistors being used in a SB core?
@split L3 subcaches:
It's simply a matter of design. You can easily switch off some of them and 4 sub caches are actually able to handle 4 accesses in parallel.
Just because I saw your post right now:Quote:
Originally Posted by stuffme
You bring in performance. Another one could point out costs (for Pł or performance/power/price also known as performance/watt/$). The next one thinks about the shareholders and brings in margins.. It's always a matter of perspective and one row of measurements is not useless per se.
so, complete die size Zambezi chip (8-cores) can be about 250-260mm?
Die size has not been released. All we have said is that an 8-core Bulldozer-based die is smaller than our current 6-core 45nm die.