Dresdenboys' blog: AMD Bulldozer - Patent based research

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Originally Posted by Chumbucket843

trace caches are a good way to utilize bandwidth. nice job keeping us updated on bulldozer mechromancer.

i am still sketchy about efficiency of decoders. do they help with CMT?

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As Mechromancer said, everything is speculative. From what I've seen and read, I think that the Decoders would suit the needs of a clustered CMT back-end. They are 4-wide with the capability to decode microcoded (complex) and fast path instructions in parallel (for 2 threads). That means up to 8 Macro-Ops per clock (4 per thread, and I found indications, that they will stick to the Macro-Ops, i.e. groups of one ALU/FP op and one AGU op). Even with only fast path instructions this would result in 4 Macro-Ops per clock being distributed alternatingly or in a different pattern to the threads, while each cluster is only capable of executing 2 of these Macro-Ops at max.

I've updated my blog with some thoughts about future power management. It seems, getting Sam Naffziger and his team into the boat was a very smart move.

ya it does......that feature (if left un-challenged) good be a game changer, especially if it preformed as speculated.

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Originally Posted by Dresdenboy

I've updated my blog with some thoughts about future power management. It seems, getting Sam Naffziger and his team into the boat was a very smart move.

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This is very interesting as you said any turbo like thing will work great with this. This can not only provide exact specs for overclocking each core independently but even other parts of the cpu.

That disapointed me in Phenom I & II, is the wide.
Core 2 was successfull i think because that was the first 4 ways in x86-64.
Just old P6 updated with the huge crash of P4.

Core 2 mixture was :
2 cores
Huge cache
( keep inclusive cache system )
4 ways
updated SSE and other instructions.

And that's all. I can say too some instructions was optimized, but the most impressive, i think that was mobile architecture with short pipeline ( not like P4 ) and ultra wide with 4 ways.

They didn't rewrited the whole work done in P6, It's insane now !!!. You must keep actual software running on your hardware, and now CPU is reaching the b of transistors. Re-write is not do able for AMD or intel without 10-15 years or work. And now we know a new real change on CPU is about 4-5 years.

AMD with bulldozer will follow the train with an wider system. 4 Wide, see the diagram, it's clear.

Other new thing are nice, like dual int, and improved FPU.

FPU was really improved on phenom, but int was a big problem.

Intel is working hard like hell, to not be over owned again by Kx. If you remember Athlon destroyed PIII with insane IPC and frequency. PIII was made on P6 architecture. K7 is now Phenom II with newer thing but the excutes units are same.

P6 was 2 ways wide and K7 3 ways.

Now core i7 is 4 ways with 2 threads / core, and Phenom II is always 3 ways.

You understand what it mean ?

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Originally Posted by madcho

That disapointed me in Phenom I & II, is the wide.
Core 2 was successfull i think because that was the first 4 ways in x86-64.
Just old P6 updated with the huge crash of P4.

Core 2 mixture was :
2 cores
Huge cache
( keep inclusive cache system )
4 ways
updated SSE and other instructions.

And that's all. I can say too some instructions was optimized, but the most impressive, i think that was mobile architecture with short pipeline ( not like P4 ) and ultra wide with 4 ways.

They didn't rewrited the whole work done in P6, It's insane now !!!. You must keep actual software running on your hardware, and now CPU is reaching the b of transistors. Re-write is not do able for AMD or intel without 10-15 years or work. And now we know a new real change on CPU is about 4-5 years.

AMD with bulldozer will follow the train with an wider system. 4 Wide, see the diagram, it's clear.

Other new thing are nice, like dual int, and improved FPU.

FPU was really improved on phenom, but int was a big problem.

Intel is working hard like hell, to not be over owned again by Kx. If you remember Athlon destroyed PIII with insane IPC and frequency. PIII was made on P6 architecture. K7 is now Phenom II with newer thing but the excutes units are same.

P6 was 2 ways wide and K7 3 ways.

Now core i7 is 4 ways with 2 threads / core, and Phenom II is always 3 ways.

You understand what it mean ?

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I say you are a bit confused. Relax, drink a glass of water and rest for a while.

Come on drop the x86 arch allready and make something new :D, jk jk.

Well i hope this will be the beast that makes Intel kneel down :)

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Originally Posted by rintamarotta

Come on drop the x86 arch allready and make something new :D, jk jk.

Well i hope this will be the beast that makes Intel kneel down :)

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many have come and tried. The problem is the value of legacy software.

I agree with both of the previous 2 posts... (NN and Rint)

x86 has been around forever, and probably a little too long... :p:

The real winner of all this would be the company who could come up with a whole new arch that could interpret x86 instructions (maintaining compatability without much performance loss)
while offering a whole new option for easier/faster code, bypassing the legacy stuff.

I'm not naive, I'm sure this wouldn't be easy, and it would open a whole new can of worms, with licenseing being the major problem!

I really think it's at least close to time though, x86/x64 are both getting a little long in the tooth....

If Dresdenboy is even close with his projections, Bulldozer might just be the chip to take us to a whole new level of performance... ;)

It's not like AMD hasn't "rocked the boat" before, one thing I love about AMD is they seem to think outside the box...

Personally I have high hpoes for Bulldozer, can't wait! :up:

2 years to wait then ...

well...only a year and a half really.

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Originally Posted by Daveburt714

I agree with both of the previous 2 posts... (NN and Rint)

x86 has been around forever, and probably a little too long... :p:

The real winner of all this would be the company who could come up with a whole new arch that could interpret x86 instructions (maintaining compatability without much performance loss)
while offering a whole new option for easier/faster code, bypassing the legacy stuff.

I'm not naive, I'm sure this wouldn't be easy, and it would open a whole new can of worms, with licenseing being the major problem!

I really think it's at least close to time though, x86/x64 are both getting a little long in the tooth....

If Dresdenboy is even close with his projections, Bulldozer might just be the chip to take us to a whole new level of performance... ;)

It's not like AMD hasn't "rocked the boat" before, one thing I love about AMD is they seem to think outside the box...

Personally I have high hpoes for Bulldozer, can't wait! :up:

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in theory it is extremely easy. The problem is selling cheaper systems with 42% more CPU performance. [to have slightly better net performance in emulated software]
And having equal or superior graphics, audio, networking, and disk performance.

Now ideally AMD or Intel can slowly shift the platform to instruction set agnostic and then simply plug the new "Uber" CPU in and patch up the operating systems; thus providing a smooth/cheap transition to the new preferred platform.

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Originally Posted by nn_step

in theory it is extremely easy. The problem is selling cheaper systems with 42% more CPU performance. [to have slightly better net performance in emulated software]
And having equal or superior graphics, audio, networking, and disk performance.

Now ideally AMD or Intel can slowly shift the platform to instruction set agnostic and then simply plug the new "Uber" CPU in and patch up the operating systems; thus providing a smooth/cheap transition to the new preferred platform.

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will never happen.....it makes too much sense ;p.

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Originally Posted by madcho

2 years to wait then ...

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it depends who you're and what you do... for some people out there only a year :D

basically all that Bulldozer needs now is 32nm tech verification! AMD isn't going to make another K10 mistake and go with old process and new architecture.
We can see now that what K10 needed was 45nm tech to show it's true value. If only IBM has perfected SOI on Immersed 45nm tech when was promised... definitely Sony and AMD suffered most 'cos of that delay.

with 32nm tech and state of things in GloFo, story with 32nm tech will be completely different, and AMD could start verification of Bulldozer uArch with first tape-out of 32nm wafers in summer 2010...

what's really encouraging is the fact that even in these hard times AMD is on track to maintain tempo of new uArch every four years... K7->1999, K8-> 2003, K10->2007, Bulldozer (K11) -> 2011

Right on time there appeared an article on EETimes about how Nvidia could go the code translation way of Transmeta:
http://www.eetimes.com/rss/showArtic...etimes_newsRSS

@madcho:
What you mention are some of the variables to get more power out of a CPU (without increasing TDP too much or not at all). But looking at the plethora of available applications (incl. games) any CPU architecture will always be a compromise. The future lies in adaptivity. CnQ or a Turbo Boost mode are just simple ways of adaption, but there is much more room to it.

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Originally Posted by Nedjo

it depends who you're and what you do... for some people out there only a year :D

basically all that Bulldozer needs now is 32nm tech verification! AMD isn't going to make another K10 mistake and go with old process and new architecture.
We can see now that what K10 needed was 45nm tech to show it's true value. If only IBM has perfected SOI on Immersed 45nm tech when was promised... definitely Sony and AMD suffered most 'cos of that delay.

with 32nm tech and state of things in GloFo, story with 32nm tech will be completely different, and AMD could start verification of Bulldozer uArch with first tape-out of 32nm wafers in summer 2010...

what's really encouraging is the fact that even in these hard times AMD is on track to maintain tempo of new uArch every four years... K7->1999, K8-> 2003, K10->2007, Bulldozer (K11) -> 2011

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Indeed depends on what you do.... AMD execution didn't fail since q4 last year, on schedule with Shanghai, ahead of schedule with Istanbul, and now on track with the new c32-g34, docs already signed, stuff heading my way really soon :D

I wonder if they've got some silicon (Bullldozer) up and running under 45nm process? I'd love to be the lucky bastard who gets to test it. :up:

[FUD] AMD's 32nm Bulldozer scales up to octal cores
Not much info here... 8 cores and AM3 r2 support, which means not all current AM3 motherboards will be suitabled for it.

AM3 r2 is to AM3 what AM2+ was to AM2. Draw the possible conclusion about compatibility yourself :)

I dont think bulldozer will be am3. C32 has a lga socket motherboard with dual channel ram, and are just server products. G34 (bulldozer) will be lga with quad channel ram, there is already pics of them floating around from cebit.

edit: oops, I guess its the other way, my bad. g34 is server parts.

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Originally Posted by To(V)bo Co(V)bo

I dont think bulldozer will be am3. C32 has a lga socket motherboard with dual channel ram, and are just server products. G34 (bulldozer) will be lga with quad channel ram, there is already pics of them floating around from cebit.

edit: oops, I guess its the other way, my bad. g34 is server parts.

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Zambezi is AM3r2 and it is bulldozer based.
You are mixing Magny Cours(2x Lisbon hex cores based on 10h) with MCM of 2x 8 core Bulldozer(server code name Interlagos).The non-mcm version of Interlagos(native 8 core bulldozer) is desktop counterpart to Zambezi,but fits in C32 socket.

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Originally Posted by informal

Zambezi is AM3r2 and it is bulldozer based.
You are mixing Magny Cours(2x Lisbon hex cores based on 10h) with MCM of 2x 8 core Bulldozer(server code name Interlagos).The non-mcm version of Interlagos(native 8 core bulldozer) is desktop counterpart to Zambezi,but fits in C32 socket.

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Informal is well informed as usual. If you want info on AMD, join AMDZone. John Fruehe himself keeps us informed. AMD is having their annual Financial Analyst Day tomorrow and they will be officially revealing a little about Bulldozer. JF says a little about it here and linked to it in his post. DON'T MISS IT!

Webcast: http://phx.corporate-ir.net/phoenix....rol-analystday

In that AMDzone thread Fruehe confirms that Bulldozer is not happening in 2010, but rather, in 2011.

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Originally Posted by terrace215

In that AMDzone thread Fruehe confirms that Bulldozer is not happening in 2010, but rather, in 2011.

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That's better then the 2012 you were hoping for. :p:

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Originally Posted by madcho

That disapointed me in Phenom I & II, is the wide.
Core 2 was successfull i think because that was the first 4 ways in x86-64.
Just old P6 updated with the huge crash of P4.

Core 2 mixture was :
2 cores
Huge cache
( keep inclusive cache system )
4 ways
updated SSE and other instructions.

And that's all. I can say too some instructions was optimized, but the most impressive, i think that was mobile architecture with short pipeline ( not like P4 ) and ultra wide with 4 ways.

They didn't rewrited the whole work done in P6, It's insane now !!!. You must keep actual software running on your hardware, and now CPU is reaching the b of transistors. Re-write is not do able for AMD or intel without 10-15 years or work. And now we know a new real change on CPU is about 4-5 years.

AMD with bulldozer will follow the train with an wider system. 4 Wide, see the diagram, it's clear.

Other new thing are nice, like dual int, and improved FPU.

FPU was really improved on phenom, but int was a big problem.

Intel is working hard like hell, to not be over owned again by Kx. If you remember Athlon destroyed PIII with insane IPC and frequency. PIII was made on P6 architecture. K7 is now Phenom II with newer thing but the excutes units are same.

P6 was 2 ways wide and K7 3 ways.

Now core i7 is 4 ways with 2 threads / core, and Phenom II is always 3 ways.

You understand what it mean ?

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agreed!
Wonder how come AMD could not come out with the same bit width with Intel C2D after they learn that the performance bottle-neck is there