Nehalem Info from hkepc

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01-04-2008, 05:09 AM
Shintai

Quote:

Originally Posted by _Lone_Wolf_

Dont off chip drivers consume very large amounts of power relative to on die buses? Elimination of a FSB link to the memory controller should reduce overall power consumption shouldn't it?

You just replace it with a higher performing CSI link to the southbridge. So no. Also the FSB itself uses very very little power.
01-04-2008, 05:23 AM
AliG

I agree, you're just replacing the bus, though it may be faster and more efficient, the actual power consumption wouldn't change that much (in fact it might go up a bit since csi runs at much higher speeds technically)
01-04-2008, 09:17 AM
Donnie27

Quote:

Originally Posted by StealthyFish

those sockets are fun. They're huge compared to LGA775 (seen em =D), and CSI has arrived =D

FSB is a bottleneck for multiple core chips. If multiple cores all share the same small bus, there's the bottleneck, not just using multiple chips.

And from what I've seen, I wouldn't expect amazing Nehelem leaked specs out since they're still pretty new.... or so I've heard >.> . You can't expect the first few bins to be comparable to retail. But CSI isn't going to be very noticable in the consumer market. Not many consumers use the full bus, but in the server department, the FSB bottleneck is a glaring problem Intel has acknowledged before. Though FSB is highly optimized, there's more potential in the chips than what's already showing.

Absolutely, currently 8.4GB to 10.6GB for Desktop and that's not being stressed. I agree with the Multiple Sockets comments, I think the Single Socket comments are blown out of proportion.

Again, I'm not saying the FSB is Good, I've saying calling it a Big weakness is a stretch at best. Sure IMC will be better than depending on the FSB and it alone would kill the FSB's biggest complaint. I know the Two Cores share one FSB link to the MC to RAM or to I/O via the DMI, I've only been playing computers since 1983. Or that the Controller Hub is just like a Network Hub with each device sucking up its portion of the total Bandwidth. Again, total bandwdith that's not being used up and latency is the only real problem.

NO, I'm not an Engineer or Coder. When I was talking about Branchey or Ramdom vs Streaming type Apps. Or games as compared Video Compression respectively.

All I care about are end results, I don't care about the inner-working of Code or Hardware. As one guy said awhile back, I don't care if the processor was powered by a Gerbil in a wheel. If that architecture argument truly meant something, AMD would be kicking the crap out of Intel with its Native Quad Core and Point to Point Topology. I also know Intel is better at Engineering than anyone posting here. They built Smart cache, Smart Memory Access and etc.. to alleviate the negative effects of the FSB/s.

I'm not sure sure how much better this will work with an IMC???

Please, note to shintai, I asked a question and wasn't arguing with you:)

Some times I think some folks "Can't see the Forrest for the trees".
01-04-2008, 11:07 AM
savantu

Quote:

Originally Posted by Shintai

You can already get 65nm chipsets today to use with your 65nm CPU. So thats basicly just pragmatics. Also I dont hope a NB uses 25W...

I'm talking about Intel chipsets.And 65nm ones have yet to be released.
Btw , a NB does use 25w.

975X uses 13w ; P965 uses 20w , P35~15w , X38 around >20w IIRC.Put that on process parity with the CPU and you cut power by 2-4x.

Quote:

If you note most of the powersavings is from a faster core. 30% less power consumption for the same performance as a Penryn. And if you have a scenario with 10-100% boost (Lowest single to highest multi). Then you have your 30% there.

The discussion was if integrating more functionality in the CPU has an effect on power consumption.Let's not derail from that.
01-04-2008, 11:20 AM
savantu

Quote:

Originally Posted by _Lone_Wolf_

Assuming the PR material is refering to absolute performance rather than a per clock figure, and Nehalem is being touted as unlocking 45nm High K/metal gate potential wouldn't most of the increase be from a clock boost, possible even drawn from the turbo mode?

..

I'd be shocked if that figure is absolute and not per clock basis.The Nehalem core is much much bigger than Penryn's , there are tons of extra stuff in the core. ( 22mm2 to 29.6 mm2 , that's a 35% increase while HT takes 5% ).

IMO , I'd expect it to give Penryn a severe beating in single threaded stuff while trashing it in multithreaded multicpu scenarios.

Intel Vice President Kirk Skaugen said the

Quote:

that the CPU core performance jump from the same process Core 2 (Penryn) to Nehalem would be higher than the jump for Netburst to Core 2 itself.

http://www.theinquirer.net/gb/inquir...halem-real-big

Remember that Nehalem is the creation of Intel Oregon , the creators of Netburst.The original Nehalem was Netburst taken to extremes , multipipelined , multithreaded everything.
I'm pretty sure some of the stuff created there got into Nehalem v2 too.
01-04-2008, 11:32 AM
Shintai

Quote:

Originally Posted by savantu

I'm talking about Intel chipsets.And 65nm ones have yet to be released.
Btw , a NB does use 25w.

975X uses 13w ; P965 uses 20w , P35~15w , X38 around >20w IIRC.Put that on process parity with the CPU and you cut power by 2-4x.

The discussion was if integrating more functionality in the CPU has an effect on power consumption.Let's not derail from that.

P965 uses LESS than 975X. I think you did like theinq in that calculation...

Also P35 uses a tiny bit more than P965.
01-04-2008, 11:51 AM
savantu

Quote:

Originally Posted by Shintai

P965 uses LESS than 975X. I think you did like theinq in that calculation...

Also P35 uses a tiny bit more than P965.

My oh my...you forget with who you're arguing.

By Intel's docs :

975X 13.5w
P35 16w
P965 19w

http://download.intel.com/design/chi...x/31015701.pdf
http://download.intel.com/design/chi...x/31696803.pdf
http://download.intel.com/design/chi...x/31305503.pdf

I was going by memory , but your "polite" reply made my look for references.
01-04-2008, 11:55 AM
Hornet331

^

thats only tdp it doesn't say anthing about the real consumption.
01-04-2008, 11:58 AM
Shintai

Quote:

Originally Posted by savantu

My oh my...you forget with who you're arguing.

By Intel's docs :

975X 13.5w
P35 16w
P965 19w

http://download.intel.com/design/chi...x/31015701.pdf
http://download.intel.com/design/chi...x/31696803.pdf
http://download.intel.com/design/chi...x/31305503.pdf

I was going by memory , but your "polite" reply made my look for references.

And a 130W TDP QX9650 also uses 130W..right?..or is it more about 55-70W?

And funny that P965 boards are the lowest with power consumption of the 3 aswell.

And just for the beating of it.
http://download.intel.com/design/chi...s/31305302.pdf

Thats what you wish to read. The Ivcc is at 7.2A substained. And the VCC is 1.25V for P965. How tell me what that result to.
01-04-2008, 01:32 PM
Donnie27

http://www.bit-tech.net/news/2007/12...gh_the_tubes/1
01-04-2008, 01:52 PM
Jimmer411

Quote:

Originally Posted by Zytek_Fan

Different socket between high end and performance? Bleh.
Unless LGA1366 is for the dual socket enthusiast platform...

Otherwise Nehalem looks like it's FTW!

Yep, once DDR3 becomes the memory standard (for Intel platforms anyway) the prices are sure to drop significantly :up:

Unless Nehalem has a "Conroe" effect on DDR3 prices like it did on DDR2 prices. I dont miss $600+ 2x1gb kits! :shocked:

3 channel DDR3? How does that work?
01-04-2008, 02:13 PM
Shintai

Quote:

Originally Posted by Jimmer411

3 channel DDR3? How does that work?

Same way as dualchannel. Nothing special, just with 3 and not 2.

Think raid with 3 disks and not 2. (Very roughly).
01-04-2008, 02:15 PM
Shintai

Quote:

Originally Posted by Donnie27

http://www.bit-tech.net/news/2007/12...gh_the_tubes/1

That article is pretty wrong in alot of places. Best ignored.

Quote:

The quad-core, "extreme" performance CPU codenamed Bloomfield, will be identical to the DP parts above, but will be single socket only and have a single QPI link. This will also be on socket LGA1366. It is suggested to have a 270mm² die size, about the same as current Kentsfield’s 65nm 286mm² die, but it’ll have nearly 150m more transistors at 731m

Yorkfield is 214mm2 and 820million. Nehalem is less than 200mm2.
01-04-2008, 02:20 PM
Zytek_Fan

Quote:

Originally Posted by Donnie27

http://www.bit-tech.net/news/2007/12...gh_the_tubes/1

Great. Bloomfield will be used to suck enthusiasts dry :down:
01-04-2008, 03:19 PM
savantu

Quote:

Originally Posted by Shintai

And a 130W TDP QX9650 also uses 130W..right?..or is it more about 55-70W?

That doesn't take into account device variation.Intel needs to take into account that , you might have a nominal 80w chip with 3 sigma variation where one chip burns 70w running a workload and another 110w.

Add the relevance of the workload and you might have real problem.Who's to say that Burn or whatever test they use fully loads the CPU ?
Intel uses in house build thermal virus and Linpack to show maximum TDP.

Anyway , that's completly off topic and I fail to see the relevance of a family TDP to a specif product from a different category..

Quote:

And funny that P965 boards are the lowest with power consumption of the 3 aswell.

And just for the beating of it.
http://download.intel.com/design/chi...s/31305302.pdf

Thats what you wish to read. The Ivcc is at 7.2A substained. And the VCC is 1.25V for P965. How tell me what that result to.

We have your assumptions vs. an Intel thermal guide. ;)
01-04-2008, 04:21 PM
adamsleath

Quote:

We basicly just need a fresh start in both CPU arch and software to leap ahead instead of doing very small steps towards the dead end.

re dumping x86 for ia64...
sorry: idea makes too much sense and has been scrapped/delayed :lol:

what is "ibexpeak"?

Quote:

Yorkfield is 214mm2 and 820million. Nehalem is less than 200mm2.

nehalem to have less cache due to IMC.
http://www.anandtech.com/cpuchipsets...spx?i=3102&p=2

re ibexpeak chipset: (on lga1160)

Quote:

Since both Lynnfield and Havendale have memory controller as well as PCI Express interconnection inside, there will be no need for GMCH (or North Bridge) on the mainboard. Instead, the new processors will connect directly to code-named Ibexpeak platform controller hub (PCH) that will carry hard drive controller, wired and wireless network controllers, monitor physical interfaces, PCI controller and other input/output as well as platform-related capabilities.

If today’s mainstream personal computers usually employ three chips that feature the core functionality of the system – CPU, (G)MCH and I/O controller – then in the Nehalem era mainstream systems will be based only on two chips: CPU and PCH. Both Lynnfield and Havendale are projected to emerge in the first half of 2009.

http://www.xbitlabs.com/news/cpu/dis...Necessity.html

still like the thought of tri channel ram:slobber: lga1366

although i wonder the advantage/s of PCH for graphics (non integrated vs integrated)
01-04-2008, 05:34 PM
Monkeywoman

i see a new build for me in Q2 "09.
01-04-2008, 06:05 PM
Donnie27

Quote:

Originally Posted by Shintai

That article is pretty wrong in alot of places. Best ignored.

Yorkfield is 214mm2 and 820million. Nehalem is less than 200mm2.

The core might be but what about all if the other stuff in the Die?

I think they may have gotten a bad translation or something. Follow their link? The layouts don't look that far off.

I should have just posted the PC.Watch link:)

http://pc.watch.impress.co.jp/docs/2.../kaigai403.htm

It's linked for reference at Bit Tech.

Another mistake on the Diags, is that there aren't two 16X PCI-E lanes. It was supposed to be One 16X, 8 X 8, and 4 X 4 from what I've read. The link clearly shows 16 X 16.
01-04-2008, 06:07 PM
Donnie27

Quote:

Originally Posted by Zytek_Fan

Great. Bloomfield will be used to suck enthusiasts dry :down:

I'm just waiting for E8500 or something similar LOL!
01-05-2008, 01:48 AM
Shintai

Quote:

Originally Posted by Donnie27

The core might be but what about all if the other stuff in the Die?

I think they may have gotten a bad translation or something. Follow their link? The layouts don't look that far off.

I should have just posted the PC.Watch link:)

http://pc.watch.impress.co.jp/docs/2.../kaigai403.htm

It's linked for reference at Bit Tech.

Another mistake on the Diags, is that there aren't two 16X PCI-E lanes. It was supposed to be One 16X, 8 X 8, and 4 X 4 from what I've read. The link clearly shows 16 X 16.

Nehalems cores are not much larger. IMC+CSI doesnt take that much space. And cache is 67% of yorkfield. Trust me. Its under 200mm2.

Also Intel would never manufactor a 270mm2+ single die chip today unless it was an Itanium grade.

PCwatch also said it was L3 cache or something earlier and other things. They aint much better.

The biggest Nehalem CPU will be an octo core at 32nm.
01-05-2008, 08:24 AM
savantu

Quote:

Originally Posted by Shintai

Nehalems cores are not much larger. IMC+CSI doesnt take that much space. And cache is 67% of yorkfield. Trust me. Its under 200mm2.

Also Intel would never manufactor a 270mm2+ single die chip today unless it was an Itanium grade.

PCwatch also said it was L3 cache or something earlier and other things. They aint much better.

Huh ? Nehalem cores are 35% bigger than Penryn's.That huge!
Nehalem is ~270-280mm^2 , you simply cannot cram 4 cores and a shared 8MB L2 cache in under 250mm^2.

Quote:

The biggest Nehalem CPU will be an octo core at 32nm.

As a matter of fact , Nehalem EX Becton 8 core is a 45nm product scheduled for mid-late 09.Intel said they will demo it this year ; there's no way it could be 32nm ( that process goes online in late 09 ).
01-05-2008, 08:37 AM
Shintai

Quote:

Originally Posted by savantu

Huh ? Nehalem cores are 35% bigger than Penryn's.That huge!
Nehalem is ~270-280mm^2 , you simply cannot cram 4 cores and a shared 8MB L2 cache in under 250mm^2.

Nehalem cores aint that much bigger. Also 4 cores and 8MB shared L2 cant be in under 250mm2? Funny since yorkfield can cram 4 cores and 12MB shared L2 into 214mm2.

And call me blind. But this Nehalem core dont seem to be Barcelona size.

http://pc.watch.impress.co.jp/docs/2...9/idf01_01.jpg

Compared with:
http://www.legitreviews.com/images/r.../barcelona.jpg
01-05-2008, 09:18 AM
savantu

Quote:

Originally Posted by Shintai

Nehalem cores aint that much bigger. Also 4 cores and 8MB shared L2 cant be in under 250mm2? Funny since yorkfield can cram 4 cores and 12MB shared L2 into 214mm2.

Nehalem has more logic as % of die area vs. Yorkfield.Also , IMC and CSI take a fair bit of space too.

Quote:

And call me blind. But this Nehalem core dont seem to be Barcelona size.

http://pc.watch.impress.co.jp/docs/2...9/idf01_01.jpg

Compared with:
http://www.legitreviews.com/images/r.../barcelona.jpg

You're not blind , but you forget that with different package sizes visual comparisons are meaningless.
01-05-2008, 09:30 AM
Shintai

Quote:

Originally Posted by savantu

Nehalem has more logic as % of die area vs. Yorkfield.Also , IMC and CSI take a fair bit of space too.

You're not blind , but you forget that with different package sizes visual comparisons are meaningless.

OK, I see. One of them obviously also got very fat fingers and the other slim.

Well you will get wiser with time...hopefully. Its a waste of time to continue.

And just for the record, its not that hard to find the package sizes....
01-05-2008, 10:48 AM
terrace215

Quote:

Originally Posted by Shintai

x86 cant improve much anymore. And thats basicly what we see again and again. Core 2 was roughly 20% faster than Core and Athlon.

Also why we have the multicore race after the ended gigahertz race.

Thats the penalty of a 30 year old design. If it wasnt for shrinks we would be seriously stuck.

So 10-25% is ALOT. AMD people should know :p:

And that's single thread IPC improvement.

If Nehalem scales to higher frequencies, you'd get a further boost.

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