That's great! Btw, my comment is also valid for socket 754/939. I just learned from your homepage that those platforms are supported as well. Memset's gotta be the most versatile tool I ever used! :up:Quote:
Originally Posted by FELIX
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That's great! Btw, my comment is also valid for socket 754/939. I just learned from your homepage that those platforms are supported as well. Memset's gotta be the most versatile tool I ever used! :up:Quote:
Originally Posted by FELIX
You can use this version: MemSet35beta.exe
DCC_EN working has been fixed.
Here is the 3.5 finale version: MemSet.exe
What news: :)
-Add support for NVidia NForce 650 Ultra & NForce 790 chipsets.
-Add support for Intel PM965/GM965 (Mobile) chipsets.
-Add support for Intel P45 chipsets.
-Add spd informations for Intel chipsets with DDR/DDR2/DDR3.
-Add some higher timings values for 965/P35/X38 chipsets.
-Add reading some frequency with AMD Phenom CPU.
-Add Intel X48 detection ID.
-Improve reading memory frequency with Intel extreme CPU.
-Improve reading Command Rate with intel P35/X38 on some boards.
Tell me if you find bug or problem...
FELIX,
Does your software configure both DCTs of Phenom in ungaged mode?
...yes, both DCTs are configured in unganged mode; it seem that you can check it with Sandra SiSoftware.
But it's not possible to change DCT A and DCT B separately.
Eventually you can do that with BAR_edit (and datasheet).
FELIX
It is possible in uganged mode easily. Each DCT has its own configuration register range.Quote:
But it's not possible to change DCT A and DCT B separately.
...yes, but not with memset.Quote:
Originally Posted by VVJ
FELIX,
I am sorry, I do not know whether your software supports Phenom, but it is not recommended to set timings for one DCT only in uganged mode. It may cause some unpredicted behavior of the system! Be careful!
I try to explain clearly:
For example, if you change tRAS to 12 instead of 10 in unganged mode with memset,
of course tRAS on DCT A and DCT B will be change.
But it's not possible to change tRAS to 12 on DCTA and 11 on DCTB,
contrary at what it's possible to do with memset on Intel chipset;
Hey Felix I have this 4gb kit and it seems to be "missing" the JEDEC spec on one
of the modules. Also on 2 out of 3 boards it only shows up as "single" channel.
One of the boards (Asus M3a) pops a message on the start up: SPD byte 23 or 25 missing. Do you have any ideas? Thanks in advance:)
Probably your spd is corrupted on Slot 1.
Byte 23 is "minimum Cycle Time at CL - 1"
Try to compare the spd of both module with SPDTool,
and eventually try to re-write the wrong spd with it.
Quote:
Originally Posted by FELIX
Many thanks :up:
The modules were like this when I opened the "box",about 2 weeks ago.
Laying on the shelf for too long could have done that maybe?
It's my first 4gb kit, if all goes well (with the tool) I might get another one as it boots @ 1066 native mode with the Phenom easily.
Thanks again Felix:)
Edit*******
Update:
It worked -like magik
a new soft: CPU-Tweaker.zip
Note that it's a new version wich support only NHM and K10 CPU (with integrated Memory Controller).
The interface is the same for both CPU, and I use WinRing0 driver now (unstead tvicport in memset).
For K10: -reading frequency is more accurate and some frequency reading was added.
-it's always possible to change Maximum Read latency, but independently for each channel.
Infortunaly, don't work in write for NHM.
Works nicely.
http://demoncomputers.pwp.blueyonder..._1.0_beta4.jpg
Operating System Microsoft Windows Vista Ultimate X64 6.0.6001 (Vista Retail)
CPU Type QuadCore AMD Phenom Black Edition 9850
Motherboard Chipset nVIDIA nForce 570 SLI, AMD K10
System Memory 4096 MB (DDR2-800 DDR2 SDRAM)
...a new build: CPU-Tweaker 1.2b4
-Enable change Core (FID) and UnCore Multipliers on AMD Phenom CPU.
-Improve Reading frequency.
-Some little change in the interface.
but I am not satisfied with this version, perhaps it's time to add a new window with advanced CPU settings.