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Nehalem is very similar to bulldozer in the way it was made, as you said from the original Pentium. The bulldozer is also made ground up as was Nehalem. Westmere and sandy bridge are additions and improvements on Nehalem "Since its modular in nature".Quote:
Originally Posted by Smartidiot89
Bulldozer will be made up in a similar way a new arc. but a base has to be there like Pentium was for the Nehalem, maybe bulldozer will be based on Am386 or K6, both are very good arc's.
You are wrong in the Nehalem's case. Nehalem is using a bit modified and improved Penryn cores and replaces the old FSB with fast point to point interconnect.There is IMC also,but the uncore part is the major change.COre part of the Nehalem design is relying mostly on Penryn's strong(IPC wise) cores and improves them with one big addition called SMT. All in all an evolution in core part with mini-revolution in I/O and memory subsystem. Similar goes for K7->K10.5.Quote:
Originally Posted by ajaidev
Bulldozer won't have the same underlying Kx architecture and will be design around totally different concept(in order to achieve maximum throughput both in int and fp workloads).The only thing that may resemble the Kx will be HyperTransport in the uncore part of the chip and FP/SSE in the core part.The latter(SSE units) will in reality still be 2x + faster than in the K10.5 due to AVX 256bit support and possibly other improvements.
why would they need a reworked core, let alone a reworked from ground up core like they said, to just add more cores?
they could do that with k10 cores... but i think we reached a point where the overall performance boost of a processor you can reach when improving the performance of each core is so high that it makes sense to rework it instead of adding more and more cores.
i really hope that the focus is on getting more perf at the same transistor budget and not keeping the same performance with a smaller transistor budget...
but looking at how things evolved in the past years, im affraid the latter is the goal, especially since both intel and amd focus heavily on the server market these days and then dump the server chips on the end users as cut down versions...
so my guess is they will go for smaller cores and possibly a new cache system and then go wild core wise and bump up the numbers big time...
for normal end users this means no real benefits though... the only performance boost for desktop would be clockspeed and we are already at 3.4ghz...
sounds like the pc industry has really slowed down and become dull... i miss the excitement of the 90s and 2000s :D
who knows though, raytracing might really spice things up :lol:
i think it has to do with how every cpu for the last n years has been built to run by itself. so for them to get perfect synergy between cpus, they needed to start over.
"...Firstly Nehalem will arrive in Q208 and is being designed from the ground up on the 45nm process. Intel has confirmed it will contain a variant of Hyper-Threading technology previously seen on the Pentium 4 CPUs, although it won’t be a hacked on addition in response to expected poor IPC and long pipeline, like it was in the Netburst days. SMT (Simultaneous Multithreading) is being optimised to make use of the many cores and shared cache in a way that “intelligently” uses the available resources.."Quote:
Originally Posted by informal
Sorce
Nehalem was a big deal to intel, the additions made to it could not be possible if the base was Penryn. The L3 in itself is a big deal AMD had to change things quite a bit of things in K10, to make L3 useful. Same is the case of Nehalem. The L3 on Nehalem is quite a bit faster than older implementations like Dunnington.
I know Bulldozer will be a different design altogether seeing Dresden's flow diagram, things are implemented differently but they use a similar methodology as other older chips like the k6. I am not saying that bulldozer will have a k6 core inside no, but it does seem that some pointers have been taken from k6's arc same goes with Nehalem and Pentium Pro.
You should stop reading into press releases and start watching at the design itself.It's exactly what i said it is. It is a mini-revolution in the IO and uncore part,that's true.But cores are just "evolved" Penryn cores,which is not bad at all since Penryn is extremely strong int performer and very good in SSE too. Its base IS Penryn,although souped up with a lot of small things and a few big ones.
Yeah im with saaya, i doubt that bulldozer will be a "ground shaking" brand new µarch. If its based on X86 it will be an evolution and not a revolution.
Just look at larrabee, based on the old Pentium core but has differnet interconnection system and follows a different design philosophie, but the cores are basically the same.
The "radical" and from the "ground up" part means that the cores won't be Kx based,but use something similar as what DDboy presented on his blog. There will be shared resources within the core,and what is a core and what is not will become a question(will a possible 2-way mini-cluster inside a core that shares the front end with other mini-cluster be regarded as a core or not? will a unified FP unit still classify the "super-cluster" as one core?).
The approach to designing this thing(from the pipeline POV) will be radically different to what AMD and intel had done in the past,and that's the reasoning behind the "from the ground up" and radical in some official statements coming from AMD that concern the new BD cores.
I have studied the design itself and i know the nehalem shares a lot of internals with Penryn like the execution engine and ROB "to a certain extend similar to P4 actually" but the LSD buffers used in Nehalem reminds me of Pentium Pro. I agree with you that Nehalem uses a lot of Penryn internals but its inspirations is derived from Pentium Pro and Dean Tullsen aka P4.Quote:
Originally Posted by informal
Bulldozer will be a very good processor if the design proposed is even similar to the real thing but i dont thing AMD will completely change how a processor works. The cache Subsystem maybe Entry>AGU>Address>L1/L2 or it maybe Entry>Address>AGU>L1/L2 thing's may as well stay the same but the size and throughput will differ.
Seems Dresdenboy has a whole heckuvalot of updates for us to read: http://citavia.blog.de/
You see what youlike and jump over (or not even try to notice) that AMDs slide CMP they already have for a long time, and now they oriented (slide:D) on cluster MT & switch-on-event MT. Not to mention that no Core2 uP (Conroe:D) doesn't even had MT at all.Quote:
Originally Posted by Smartidiot89
And that would mean even core level offload and partial sleep of active core. Core2 & Nehalem afaik were one global core that share same functionality while we here (judging by patents) have 2x integer unit for some reason (switching of during low load one or both units) and heavily threaded FPU (3 FPU with 3 threads?). So threading is only where it's really needed ... on the FPU. But we still need Integer units for load/store into memory. Does that reminds on something :p: Anyone. Some more advanced form of intels Larabee with 64bits x3 FPU x3treads .... it could pretty much reach 320b-384b utilization i guess.
And all that stuff about interconnects ... HT, NB/SB IC (pcie,sata,network) , cross-point switch, bridge. These will really be purely SoC by design. And all AMD needs then is to segment market, and oriented itself to improve HT execution for multichip servers on it's next architecture iteration, or it will be already there to humiliate newly designed Intel's QPI :rolleyes:
Found this post over at AMDZone from a German site and thought it might be of interest. The road map shown is purported to be 'internal' and shows new code names for a 32nm desktop processor - 'Zambezi' (nee Orochi?), a platform "Scorpius', and Socket 'AM3r2'. If true, this seems to indicate that Zambezi will plug into the current 941 pin AM3 socket and may be backwardly compatible.
The name Zambezi is also interesting - one river (core?) with four mouths (threads?). Look it up (I did) - could AMD be saying something with the name?
http://translate.google.com/translat...istory_state0= - scroll down 11 items.:D
Hmm, Llano is the name of a river too.
lol, AMD moved from calling it a eight-headed serpent who demanded virgin sacrifices "Orochi" to fourth-longest river in Africa "Zambezi"... Why??
Orochi sounds much cooler and aggressive, if AMD is telling us something by names you can expect the new Bulldozer architecture to be smaller than other architecture "4th longest river" and well cold "rivers are cold because they flow" :):):):) Just kidding
EDIT: The platform could be called serpent!!! :)
http://ht4u.net/news2/news_images/am...p_bis_2011.jpg
Nice to see BD platform is AM3 derivative,an AM3+ that will resemble the AM2/AM2+ transition. In effect,BD cores should be able to slide in AM3 boards but not AM2+ ones,probably due to IMC which will be DDR3 only(this is my speculation of course). AMD is hinting about the core capabilities,the sme ones Dresdenboy wrote in his blog :).
Llano on the other hand is not BD derivative but a K10 on a 32nm with integrated GPU on a same die,as said by AMD themselves(AMD at work blog post). This part should have its own socket,different from sAM3+.
Some info on AMD's code names from the 'horse's mouth', as it were, over at AMDZone.
From JF's description, it appears that 'Zambezi' is the name for the desktop 32nm. If 'Orochi' is just a single core, as stated, the implication boggles the mind. Eight headed (threaded?) snake/dragon!:eek: I'm may be reading too much into the names - probably just a name without any hidden meaning.Quote:
Postby JF-AMD on Sat Sep 26, 2009 4:09 am
Well you have to keep in mind that there are project code names, core code names, processor code names and platform code names.
Bulldozer is the project to overhaul the core. Orochi is a core. A modified orochi core will be in an Interlagos processor which fits in a Maranello platform. And there is an overall project name that I will not reveal.
While I work for AMD, my posts are my own opinions.
http://blogs.amd.com/work/author/jfruehe/
nice one, with roadmap !
well it looks like thats a trend in their code names. "bulldozer" is a complete redesign so i think orochi could imply CMT or maybe it has to do with some other part of the architecture.Quote:
Originally Posted by RiverRicer
Yawn. Less chitchat, more benches.
Can't bench what you ain't got yet!:D
maybe because they're taking their time with the design of a new core. hence 4th longest lolQuote:
Originally Posted by ajaidev
and river for the flow and rate they're going at.
Kinda my point. ;)Quote:
Originally Posted by RiverRicer
A Loop/Trace Cache like Sandy Bridge?
Quote:
Return of the trace cache (or: trace cache done right)
by Dresdenboy @ 2009-10-02 – 07:46:31 pm
According to Andreas Stiller from german c't magazine (in German), Sandy Bridge will have a loop cache with space for over 1500 µOps (1536?) compared to Nehalem's 28 µOp loop stream detector buffer. This will actually make it comparable to a trace cache. A Wikipedia article about Sandy Bridge's architecture mentions both the trace cache and a "16 KiB decoder" (decode cache?). These two seem to be the same and are actually comparable to the loop cache. Some plausibilisation: 16 KiB could be enough for ~1500 µOps (more than 80 bit/µOp). As it seems, the data presented in the Wikipedia article has been collected from older Intel presentations, but I didn't track that down to the original sources.
As I wrote in earlier blog entries Bulldozer might have a trace cache or a "redirect recovery cache". Most of the described variants work in the same way as Intels loop cache. To me it seems likely that Bulldozer will that too. This is not just a matter of performance but also of power efficiency. Using a trace cache is a way to reduce power consumption, e.g. by reducing the work to be done by the fetch and decode stages. Additionally some code optimization/instruction combining of the traces could be done in the non critical path. Such a method has been described in one of the older patents.
trace caches are a good way to utilize bandwidth. nice job keeping us updated on bulldozer mechromancer.
i am still sketchy about efficiency of decoders. do they help with CMT?
Heck, we don't really even know if CMT will actually be implemented yet. It's all speculation at this point. Still, it is good to know AMD is hard at work engineering advanced features into their products. Unlike Sandy Bridge, AMD will actually include support for Fused Multiply Add (FMA). Click that link to read about it over at AMDZone. Bulldozer has a fighting chance to be a Core 2 to Intel this next round. Lets just hope there are no more delays or business issues keeping that from happening.Quote:
Originally Posted by Chumbucket843
Fiorano and Kroner were also shown a few days ago and I didn't hear about that here on XS either. There is a lot of news coming out of AMD these days.