your own goddamn link said its 15% faster clock for clock...
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your own goddamn link said its 15% faster clock for clock...
No I think it would be safe we all assume it will be slower than the K8 :rolleyes:.Quote:
Originally Posted by cky2k6
We can't be wrong with that...
OTOH,on the serious side,one would assume a greater degree of performance boost than an average of "your 15%".
Considering the: doubled SSE and FPU units(FP scheduler was widened from 64 to 128b),separate power planes for the CPU and Northbridge(more aggressive clocking),more efficient memory use-the two memory controllers on the chip act independently and hit two memory locations at once, better caches,better branch predictor(bigger and better with a larger history,a dedicated 512 entry indirect predictor and the return stack is doubled in size.), virtualization and power management,instruction fetch was upped from 16B/cycle to 32B ,support for unaligned load ops was added and cache bandwidth was doubled to support this,new mem.controller(increased buffers and adding support for new DRAM types),native 65nm design,sideband stack optimizer, out of order load execution and data dependent divide latency,the TLB upped to support 1G pages, 48-bit physical addressing, and improved the ITLB and DTLBs;more fastpath instructions ,a few more bit manipulation instructions and SSE extensions.,shared L3 in both quads and dual cores... etc.)
This all sounds as it's a bugger core and will be the whole 15%!!! overall faster .AMD may as well sell of it's fabs right now. /sarcasm
On top of what Informal written I want to add HT3.0 interconnections and higher clock speeds (than K8, DualCore version at least) before end of 2007!
My bad, but atleast its capable of some nice stock speeds later on. And have almost 50% higher FPU's then the older K8's because they doubled it per core in K8L. This will mean K8L Will be a mean media encoder. However IBM is way ahead of anybody with Cell and the new Power6/7's.Quote:
Originally Posted by cky2k6
But we don't know the total performance hit until the parts are actouly benched.
unfortunately, penryn is rumored to be capable of the same nice stock speeds, except it will be released at them, while k8l will only eventually hit them. amd will probably find its way to the top again with fusion and gain a few percent when 64bit becomes the standard.
Every company releases the slowest part they can at the time so the new arc will last a decent amount of time. its always been like that since the FX-51 to the FX-76 after 3 years. The stock limit for K8 is 3.2ghz. Wile the K8L maybe 3.5ghz or higher at some point. Or might be quickly replaced by fusion.
But fusion is totally new territory that won't add small numbers to a benchmark, it can't even be thought of in the same legue as a cpu because its not even a cpu but a CGPU hybrid and can do things a cpu alone can't. Or whatever you want to call it. It will be the next big leap like from going to having no memory controller at all in the cpu to having one, or from going single core to dual core was like revolutionary or from going 16-bit to 32-bit was huge. Thats what fusion is a new standard. They already have the PCI-E controller in there, not much left to add thats major. =P
well if I read correctly 3ns Response times, is a good deal better than DRAM and The small cell size leads, in a roundabout way, to Z-RAM being faster than even SRAMQuote:
Originally Posted by Shintai
Stop dreaming about fusion it wont be here until 2010 and even then primarily for laptops.
http://www.infoworld.com/article/07/...ergence_1.html
And your my mother? =PQuote:
Originally Posted by xmax
Z-RAM runs at the same clock speed as the cpu in later ver's right? Or will they even do that with K8L on just S-Ram. There are other types of cache better then S-Ram they can use.Quote:
Originally Posted by nn_step
well actually I think they say it best http://www.digitimes.com/bits_chips/a20060328PR202.htmlQuote:
Originally Posted by Serge84
I'm actually curious about one thing though from Intel, the Stacked Cache. (where the processor is ontop of the Cache) I'm wondering if there is a patent about that because if not, then AMD could use it with Z-Ram and under the Quad cores, they could have about 20MB of L3 :slobber: (Cores the size of K8 dies with 512kb L2 of course)Quote:
A Z-RAM bit cell isn't as fast as an SRAM bit cell, but there's more to memory than just bit cells. In addition to bit cells, you have row decoders, sense amplifiers, muxes and so on. So the delay in deep submicron circuits is really driven by interconnects and metal lines, as much as it is by the transistors and gates of the device itself. Since Z-RAM is much denser than SRAM, where the memory block is very large, you can actually see the relative difference between SRAM and Z-RAM shrinking. SRAM starts out as a faster technology, but as its blocks become very large, Z-RAM starts approaching the speed of SRAM
Also, what happens if AMD drops SOI? ZRAM becomes useless.
And again, ZRAM will NOT see any product soon.
AMD has licensed the second generation Z-RAM to research it for potential use in their future processors.
So it´s simply another toy in the lab to play with, should it become useful for anything. So ZRAM and K8L is a not even realistic, even if they choose to start using ZRAM.
It´s amazing how unrealistic things get hyped up. From something they barely research to someone already starting to talk about it in the nextgen products. Talk about 2 eggs that end as 5 chickens before the story is over.
3ns? Thats pretty slow for any type of cache. And just look on the disaster with added latency to the 65nm K8.Quote:
Originally Posted by nn_step
The new 3.2Ghz GDDR4 samples (DRAM) got 0.6ns access time. Just to show something to compare with.
Lets drop this ZRAM talk and look at it again in 3-5 years when it might have become useful. Or just buried like so many other things, that was told to yield incredible results.
AMD IS dropping SOI for SSOI for K8L. Thats whats happening, they are taking IBM's road down the better path.Quote:
Originally Posted by Shintai
Or even this path. (SGOI) A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed. And would be one hell of a process for performance.
The cycles are only 12 on K8 90nm and 14 on K8 65nm not much of a difference. But if set to 3 that would be insanely fast.Quote:
Originally Posted by Shintai
Why don't they just use XDR-RAM or XDR2-RAM dies as cache in place of S-RAM or Z-RAM? I know how insane that is but XDR-RAM is insane ram specially if used as cache at the cpu speed because its capable of it. It would eleminate all latency problems they would have.Quote:
Originally Posted by nn_step
Quote:
Originally Posted by Shintai
well there are a couple reasonsQuote:
Originally Posted by Serge84
1)XDR takes a good deal more die space than SDRAM (aka Regular Cache) and has worse latencies
2)I was referring to actually work time (which GDDR4 is well over 40ns if you actually notice)
3)20MB of cache at 30 clock cycles still perform a hell of alot better than 2GB of ram that take well over 100(this is a gross estimate for a 2Ghz CPU)
4) SSOI is Strained-Silicon-on-Insulator which is a higher performance version of SOI :fact:
5) No matter what AMD does or doesn't include in K8L, it still should be one hell of a beast
first you are saying that we cant talk about K8L's performance, and now you say, at that clockspeed amd will be in a lot of troubleQuote:
Originally Posted by Fred_Pohl
way to go fred,keep up te good work :slap: :slap: :stick: :stick: :clap:
No serge, unless AMD themselves dont know what they talk about. AMD said that K8 65nm is 20 cycle. Also, 3ns is NOT 3 cycles.Quote:
Originally Posted by Serge84
http://www.anandtech.com/cpuchipsets...spx?i=2893&p=3
Dont make up stuff again. You seem to have trouble putting reality and your dreams aside.Quote:
Originally Posted by nn_step
Actually work time? You do know that with 3ns worktime, the read request alone would be 3ns if a single cycle and 400Mhz? So seriously, stop the FUD.
Either you are blinded by your wishdreams, or you simply dont understand it.
according to lostcircuits the L2 latencies are not much bigger on 65nm than on 90nm, and that's probably cause they're testing possible K8L options it the short remaining time till its launch.Quote:
Originally Posted by Shintai
http://www.lostcircuits.com/cpu/amd_65nm/12.shtml
fixed link.
http://www.techreport.com/onearticle.x/11486Quote:
Originally Posted by alayashu
Your link gives a 404. And 66% higher latency is alot bigger :P
Specially when you want to play games...
http://www.firingsquad.com/hardware/...view/page5.asp
A 100 MHz (4%) increase in clocks countered by a 66% increase in L2 cache latency AND a 11% decrease in memory clocks with its associated latency issues and making it perform 5-12% slower in games.
Better off lowering the 1/2 mutliplier to retain normal ram speed, and crankign the fsb up. AMD should be using a 266 DDR2 bus anyway. No reason why not. What FSB structure is K8L using?
Quote:
Originally Posted by GoThr3k
I never said that you can't talk about K8L's performance, I said that doing so is much like trying to tell the future by gazing into a crystal ball. :stick:
As for my clock speed comment, if K8L launches at only 2.1-2.5GHz, as the poster to which I was replying indicated, AMD will be in a lot of trouble. Unless of course you believe that K8L will be over 50% more efficient per clock cycle than K8, which I do not.
Quote:
Originally Posted by Serge84
:confused: From the AnandTech article you link:Quote:
Originally Posted by Shintai
"Although AMD previously did not mention any issues with our findings, we were contacted today and informed that the latency information both ScienceMark and CPU-Z produced is incorrect. The Brisbane core's L2 latency should be 14 cycles, up from 12 cycles and not 20 cycles."