DFI has memory problems though. this may look like the new solution for overclockers.
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DFI has memory problems though. this may look like the new solution for overclockers.
great news for BH5/UTT guys
what are the dividers like with BH5 ram....can you do say 310*9 with 166 divider or 310*8 with 166 divider
shame about TCCD......might need a bios bump or something....it's a bit concerning
IS THIS THE Ultra Board you've got there.....pretty cheap too in Australia
http://www2.abit.com.tw/page/au/moth...Specifications
Quote:
Originally Posted by Sheik
tictac you heard any word on the AN8 Ultra ??
http://www.abit-usa.com/products/mb/...es=1&model=278
I like it cuz it has passive heat sink. But I can't find one in USA nor a review.
yeah... that is my next board :hehe:Quote:
Originally Posted by Zebo
solo just confirmed that board also has 3.5v max vdimm :woot:
not availabe in Indonesia yet :slap:
but you can get it in USA : :banana:
http://www.unitedmicro.com/mbw.cgi?153222835
nice
I'm looking at buying one as well
stock has landed in australia recently for AN8 Ultra, AN8-F, and AN8 fatality
not sure on AN8 v2.0 but I'm still waiting on a reply
what are the dividers like with BH5 ram....can you do say 310*9 with 166 divider or 310*8 with 166 divider
I'll give it a bash with the AN8 non-Fatal1ty SLI :D
Yes I have both the AN8 Ultra 2.0 and AN8 non-Fatal1ty SLI 2.0 :p:
Oh and the Abit AW8-MAX Intel 955 LOL Can't believe South Africa got stuff before Indonesia for a change :woot:
ordering the an8 ultra today will give it a run with 4 different pairs of ram when i get it.
mushkin pc3200 (bh-5)
mushkin pc3500 (bh-5)
gskill f1 la 4400 (tccd)
mushkin redline (bh 5's kid sister)
will give you results soon. If its anything like my fatality was i think ill break my old htt record for abit nf4 boards :)
Mushkin and Venice comes in today! Can't wait to see what this ram will do :)
wow.... :clap: thanks ...Quote:
Originally Posted by bigtoe
keep us posted &
maybe you can provide us some memory timing tweaking guide for TCCD with this board later... :woot:
tweaks found hereQuote:
Originally Posted by tictac
http://members.cox.net/italygirl25/tccd.bmp
failed prime at the 23 hour mark however my clawhammers memory controller is kinda :slapass: etc at 10 X 240 with bh-5 passes prime stable however 8 X 300 it would fail after about 23 hours. tccd was not at fault as i looped memtest for 2 days at those timings no errors.
how about Winbond UTT settings for those (like me me) who have Mushkin Redline XP memories?
great let us know
Quote:
Originally Posted by chew*
hey if anyone has 1T issues with this baord and Venice, please post so I would know its me and not the hardware. Thanks.
I´m having troubles with 1T... it makes my machine turn off
Page 1 will be update from time to time with usefull info... ;)
http://www.xtremesystems.org/forums/...96&postcount=1
ukveld... what board you running on? Spec? Coming from Intel? :hehe:
yeah... back to the dark side of the force ;)
Specs:
Abit Fatal1ty AN8SLI
A643200+Venice
Mushkin Redline XP3500
XFX6800GT
XP90c
@ over 250~260HTT i get that same problem with 1T... tried 166Ram divider without any luck...
maybe time for a tictac modded bios to solve that problem :D
that would be awesome :)Quote:
Originally Posted by ArcTan
i get that auto power down problem at stock! lol
ok... just leave that 2T option in bios
after windows load change it back to 1T with a64 tweaker... see if it freeze / power down again...
waiting........... :)Quote:
Originally Posted by chew*
is that how everyone got 1T to work? or at least most people?Quote:
Originally Posted by tictac
the first time it froze instantly... second time it worked fine.... Abit needs to enhance this bios it seems :) i love the look of this board ;)Quote:
Originally Posted by tictac
another 1T probsie
i wonder if Ultra guys will experience the same problem....this is starting to look like my board :lol:
Quote:
Originally Posted by ukveld
This might be fixed as it could be a bios issue and the board is out for a few days, some ppl don´t have any problems so i´m hoping the next Abit bios (or tictac moded :)) will fix this soon.
good thing it doesnt really degrade performance by a whole lot, maybe 1 or 2 percentage.
2T will drop 30MHz in performance....read it somewhere so if you are only losing 2% you are actually either running 2T or 1T and not comparing the results properly.............where do you get the info for 1T ONLY or 2T ONLY At all times....bios OK...what about windows...SiSoft, A64Tweaker?!?
PLS beware that Sisoft Sandra actually reports 2T for all 1:1 settings regardless....bug in the software....if you are running a divider at 1T it will show it properly......A64Tweaker gives reliable settings......
Look i don't want to be a party pooper but asus guys have been waiting for a bios fix for 1T 250MHz ceiling since late last year and it still hasn't been fixed.....BUT as you said it actually works good on some machines and doesn't on others so it is promising
SOLO...since you run yours at 1T(i assume so) please let us know of the full setup so we can figure out or mimic this problem with other users......I think Solo is using the FX55 for his tests which may very well work better with these bios files as it is an older core CPU......it seems Venice CPUs are plagued with that problem ATM......
I read the first page but i couldn't see anyone running high multiplier stable at 300+HTT at 9,10 multipliers........week 17 3000+ venices are all easily doing 2800MHz which is 311*9......can anyone test if this board can do that or not.....
Quote:
Originally Posted by situman
i'm shooting myself in the foot here...:slapass:
i just did some more research and came across this forum thread which confirms that the difference between 1T and 2T is 3% at most........except for SiSoft Sandra which doesn't really reflect real life performance anyhow
I would still reserve my judgement on video encoding jobies which i didn't see get much mention but it seems that 1T or 2T CMD rate will not really be as bad as i thought
http://forums.anandtech.com/messagev...VIEWTMP=Linear
Knew this myself after running a few simple tests.
1T v 2T means jack :banana::banana::banana::banana: in real world preformance - 1 to 2%, the only thing that shows a dramatic gulf between 1T and 2T is sandra bandwidth test....and we all know that to be a BIG wank which mean nothing at all. :fact:
OK two things:Quote:
Originally Posted by dinos22
Setup is:
Abit AN8 SLI Fatal1ty Athlon64 Socket 939 motherboard (BIOS 13)
AMD Athlon64 FX55 (130nm) processor
Mushkin (Winbond BH5) DDR433 (2 x 256MB) / PQI Turbo (Samsung TCCD) DDR400
Secondly the AN8 SLI (non-Fatal1ty) with heat pipe also has 3.55V and all the other options in the BIOS of the AN8 Fatal1ty SLI and Ultra with heat pipe.
I run 1T no problem.
OK...i would lean towards CPU support here...even though bios 13 supports venice it probably needs a bit more work....thanks bigtoe...i'm sure there's a contribution there already
i ordered the AN8 Ultra and will get it tomorrow to pair up with a 3000+ Venice 0517EPMW that does 2.8GHz stable at 1.52V.......i'll keep you guys posted about this....CPU was checked out in my asus board which i sold yesterday and it did 32M around mid-26m in 133 divider...so ram was 200MHz 2-2-2-5-1T...the CPU would probably top out in the 2.85/2.9 on air i'd say......Ultra mobo will have to go way past 300 to keep up with this CPU....
Quote:
Originally Posted by Sheik
it seems that the problem is venice only... or myb san diego too?Quote:
Originally Posted by Sheik
i´ll do some further testing, hope Abit grants us a new bios soon...
@ default i can do 1T without any troubles :)
Running now @ 300x9 with memory @166divider and still testing :)
that's what i want to see....that is the new UTT ram isn't it
Quote:
Originally Posted by ukveld
Solo dude.....let us know if you can run that nice BH5 RAM in divider at high FSB like ukveld is doing.......
Quote:
Originally Posted by Sheik
:( Not enough Vdimm at all - I need at least 3,72 for specs shown in SIG.
:toast:
Yea need like 3.8 for my BH5 Abusing @ 285Mhz.. :D Nice board stable and all.. :D i don't think DFI will put another 4V VDIMM option again, or they will make it optional, ect causing to much major problems for them.. Abit being sensible actually :D
what is the latest bios for this bios?
tictac, I've seen BIOS 13/14 uses previous CPU microcode, so I guess updating it would improve Venice/San Diego support ?
Quote:
Originally Posted by ReelMonza
same microcode? bios 14 is for SLI aswell? any improvement would be welcome :)
you would be better off with Abit + booster....or maybe DFI can resolve this problem with their boards with new revisions.....
Quote:
Originally Posted by HARDCORECLOCKER
Quote:
Originally Posted by Jasonhk
I think so.Quote:
Originally Posted by ukveld
CPU microcode update is easy to be done but I'm not sure if it would help anything.
i wouldn't try a booster on this board. it's getting the vdimm from the 5v line.
dfi is getting the voltage from that line with that jumper but if you're using the booster on DFI you'll drop it back to 3.3V line of course
if you are suggesting Abit vdimm voltage option is actually off 5V line I didn't know that.......please make it crystal clear what you meant there.....
can any of you Abit gurus confirm which line is used for RAM on these V2.0 boards with 3.55vdimm option in bios
Quote:
Originally Posted by esoteradactyl
how else are you going to get more than 3.3vdimm?Quote:
Originally Posted by dinos22
well if the max vdimm is 3.5v, then obviously the vdimm is not being supplied by the 3.3v rail. your psu 3.3v rail would need to be modded in order to get more than 3.3v. if the booster works on the dfi when the jumper is set in 5v mode, that's a new one on me. maybe dfi has something special there. im pretty sure every board that uses the 5v rail to supply vdimm is not compatible with the booster.Quote:
Originally Posted by dinos22
my bad
booster works with DFI yeah
Quote:
Originally Posted by esoteradactyl
i wouldnt reccomend the booster on the board and not because of 20 pin psus etc there are adapters however when i messed around with my fatality it would not even post with it installed. which is why i went with a hard mod which eventually toasted something on my board. etc my board still works however the vtt reads 4.0 v and vddr reads 4.2 v and initially after i damaged it i had to give the psu a jump however now it will turn on via power button after the initial jumpstart.
hi m8
did you give it a bash...also why not try ultra as well....anyway i guess any 3.55vdimm board will do a similar job
Quote:
Originally Posted by Sheik
Just tried the 1.4bios without any change on the 1T/Venice issue... oc seems more stable :)
well I would prefer the regular SLI version due to higher resale value when you want to sell it back.
You mean like so.Quote:
Originally Posted by dinos22
i had to rma my msi board, and i would gladly sell it if the abit board is a better overclocker? more options in the bios?
also where is everyone getting their a8n ultra's from?
ultra not in stock near me so i picked up the sli board some results later gott install it now.
http://www.xtremesystems.org/forums/...chmentid=32607
Looks like they are using ISL 6559CB as a Vcore regulator (Vsense Pin13) :hehe:
and Sanyo Oscon Caps behind the Vcore mosfet heatsink :woot:
Copper Heatpipe :clap:
Hello Everyone,
Ok, I ordered my Fatality SLI, will receive it on Monday. Will assemble, and run some mem tests in the eve (South African time)
Will use it with FX55 130nanometre cpu, and Mushkin BH5 3500, OCZ Rev2 TCCD (Brainpower pcb) memory. My Mushkin and Solo's are about the same, his a little stronger, based on previous experience, but I will anyway post my findings to see if I can run 1T with Mushies and FX55, and if indeed your issues are related to Venice.
Keep tight, with luck I will have my new mobo Monday. Currently DFI-SLI-DR...in case you wondered.
Enjoy the weekend,
MrBean.
i got an an8 sli with a venice and have the same 1t setting problem cant even run it at stock. i also have a problem with the ide 1 when my hard drive is conected to that windows wont install (errors and things show up) but when i use a sata converter it works fine. im using kingston hyper x bh5 for mem not sure if that has anything to do with the 1t problem.
Ah it's Mr Bean :toast: hehe.
Well I got a new best of 265 MHz with the plain AN8 SLI board :banana:
Hey Sheik-Solo,
Good to be here :)
Seth managed a board for me, new place in Durban, so I should have it Monday.
Good going on your memory, mine maxed out (bench stable) at around 263 on the DFI, with Vapo that is where I managed 26.53sec SuperPI.....I just hope that this board is not tweaked so slow in the Bios that it is merely an theoretical higher o/clocks the guys seems to be getting on memory?
Same issue with the latest DFI-SLI's, maybe the batch we have back home, rra's been complaining that he dropped 1/2-3/4 sec in SuperPI with all else being equal...mmm...now have to run close to 100mHz higher on his FX55 to get same SuperPI times....
But yeah, as I said, will see what I can tweak from this board, and compare it to my DFI. Will keep cpu stock, and record some SuperPI times on the weekend. I still have 2x 512M of the Twinmos BH5's as well, so I can do some thorough testing.
Chat to you later again.
New bios out... 1.5 for AN8 don´t know if it works ok on SLI, seems correct thought.
ftp://ftp.abit.com.tw/pub/download/bios/an8/an815.exe
source: http://forum.abit-usa.com/showthread...524#post575524Quote:
Release information:
[ENGLISH]
1. Update MCT2
2. Support dualcore cpu
3. Modified DMI Pool
4. Add ACPI CPU1 data
5. Delete ¡¨an emergy star¡¨
by: dboss77
Just tried it... my cpu temps are really high (50ies) and can´t boot with my previous oc... reverted back to 1.4bios. Bad job Abit!!! :slapass:
i like
Quote:
Originally Posted by Sheik
hey bigasstoe any chance of telling your Abit bios mates to also include 150 divider in there...kinda important for all of the 3000+ venice guys with CPUs capable of 2900-3000.......it would be nice to have UTT ram running somewhere between 133 and 166 divider............unless someone can figure out how to unlock A64 :toast:
ok windows and all updates installed default settings in bios and all seems stable. figured id run some tccd first since you guys cant seem to find the 300 mhz sweetspot. heres a little idea of the setup for now.
an8 sli
3500 clawhammer
2x256mb f1la tccd(also 2x256mb mushkin pc3200 bh-5 and 2x256mb mushkin pc 3500 bh-5)
x800xl
antec neo 480 psu
wd 36gig raptor(wd 7200 80gig)
asetek waterchill pro( 3x120 radiator)
thermaltake tsunami case
I've installed the ramslot cooler from my fatality board as i think this one can utilize it more :)
first impressions are that abits temps are still way off no way a asetek waterchill pro is running this cpu at 117f at idle
second impression is that although the heatpipe works good although i still think that this board can benefit from water on the nf4 chip as it runs extremely hot, hotter than my fatality IMO. I think when my chilly 1 chiller arrives sometime in the next week or 2 im going to run the asetek on the nf4 chip. will have some results in a bit need to download some bench utilities.
Can't wait to see that Mushkin BH-5 tested, chew*. I've got 2x512 of the PC-3500.
ok first goal was to break my old stable htt record and it was a cinch 395 htt.
i ran a super pi 1 mb test while priming a blend torture test neither crashed i'd say thats stable not only that but it was a breeze to reach it im sure i can go higher but i'm going to screw with the tccd now.
settings for screenie were 395 htt with a 2.5 x multi ddr at 200 6x multi on cpu no voltage bump for htt or nf4 chip.
http://members.cox.net/italygirl25/395fsb.bmp
:clap: ... that is abit htt record so far... awesome job :up:Quote:
Originally Posted by chew*
anyway can you make a screen shot on Gif or jpeg... that will save your server bandwith / help 56k user like me to view it :slap:
here i teach you how.. :sofa:
- press printscreen button(keyboard)
- then open microsoft paint
- paste it there
- save it as Jpeg or gif
24bit bmp is way to big .... :slapass:
395.5MHz HTT....very very nice.......
yeah that bitmap is not a good idea....even cable takes few seconds longer than it should :slapass:
your CPU is capable of 2.8GHz....why don't you try 7x multiplier
abit record # 2 heres some tccd results memtest stable 3 passes.
http://members.cox.net/italygirl25/tccd%20315.bmp
and ya ill turn them into jpegs next time.
BMP again :slapass:
Quote:
Originally Posted by chew*
OMG 315*8 1:1 TCCD 1T :slobber:
.............................
Thanks m8.... :up:Quote:
Originally Posted by dinos22
:woot:...chew* as ABIT HTT & TCCD max record ... :YIPPIE:
waiting his winbond result next... :worship:
ha ha ha
you grabbed my partial post there.... :lol:
Quote:
Originally Posted by tictac
ok... new result added in 1st page:
http://www.xtremesystems.org/forums/...96&postcount=1
Where is your board & result? :nono:Quote:
Originally Posted by dinos22
i am peaking cause the courier decided NOT to drop it off on friday and do a monday run instead so i have to sit it out until monday before i hopefully see this board.....hopefully some initial results on Tuesday
I will play with
A64 3000+ Venice 0517EPMW does 2.8GHz easy
Corsair Twinx1024-3200Cv1.5 UTT RAM...did 237MHz stable 3.2V on DFI nF4 Ultra-D
Corsair Twinx1024-4400C25 TCCD RAM...did 300MHz unstable 2.9V on DFI nF4 Ultra-D......unstable primarily because of my old 3000+ Winchester unable to run over 2650MHz
Quote:
Originally Posted by tictac
heres a sucide shot on sandra memory is stable but cpu isnt. this cpu really needs some phase loving i forsee 3.5 gig on phase or a cascade.
http://members.cox.net/italygirl25/sandra.bmp
................9xmultiplier.....1.8V :frag:
Quote:
Originally Posted by chew*
hey any bh5/6 results and settings? I dont have tCCD to play with. NOT FAIR!
Quote:
Originally Posted by situman
as u wish
mushkin pc 3200(heatspreaders not removed) 3.55 vddr 1.75 vtt timings in order from top to bottom
2-8-12-2-2-5-2-2-1-1 1t. I do not back off timings in order to acchieve higher speeds these timings are the best for performance and lowering them in order to gain mhz is kinda useless.
http://members.cox.net/italygirl25/bh-5%203200.bmp
is that a venice core? U dont seem to have the 1T issue and it seems to only effect the Venice or even the Sandy.
clawhammer :)Quote:
Originally Posted by situman
heres some more bh-5 same ddr speed higher clock to show you some nice scaling of performance with the timings i use. this memory is 100% stable at this speed with these timings looped memtest for a couple hours no errors
http://members.cox.net/italygirl25/more%20bh-5.bmp
i thought super tight timings are
2-7-12-2-2-5-2-2-1-1 1t
read write queue bypass 16x
bypass max 7x
max async latency 6ns
read preamble 5ns
sort of but im going by timings allowable in bios without a third party software.Quote:
Originally Posted by dinos22
sheik ill see your 266mhz and raise you 2 :)
timings by spd in bios swapped it to manual and left them what they were.
mushkin pc 3500 bh-5 heatspreaders still intact. I think ill take the heatspreaders off this set seeing how they seem to have more potential.
http://members.cox.net/italygirl25/3500@268mhz.bmp
shut the gates chew* is on a mission
awesome results....show us what the A64Tweakers settings are like there
Quote:
Originally Posted by chew*
So far i able to build this source code as my A64 memory timing patcher through bios level...
Anybody have Dimm Dram Drive Strenght & Data Drive Stregth as DFI bios please let me know where it is located.. i'm not able to find it :(. Please correct me if you find any bug on my source code
I hope abit can add in more memory timing in future bios of this board... :(
ISA ROM Patch Source Code
Code:;---------------------------------------------------------------------
; tictac A64 Bios Tweaker Rev 001 Alpha
;---------------------------------------------------------------------
.486p
CSEG SEGMENT PARA PUBLIC USE16 'CODE'
ASSUME CS:CSEG
ORG 0
;---------------------------------------------------------------------
; Expansion PCI ROM Header
;---------------------------------------------------------------------
db 55h ; Rom signature byte 1
db 0AAh ; Rom signature byte 2
db 01h ; Rom Size (1bit = 512 bytes)
jmp INIT ;jump to initialization
;---------------------------------------------------------------------
; Address & Data Port
;---------------------------------------------------------------------
address equ 0CF8h ; Access to configuration address
data equ 0CFCh ; Access to configuration data
;---------------------------------------------------------------------
; PCI Bus, Device, Function, Register
;---------------------------------------------------------------------
; _________________________________________________________________
; | 28| 24| 20| 16| 12| 8| 4| 0| Bits Number
; |1 0 0 0|0 0 0 0|0 0 0 0 0 0 0 0|0 0 0 0|0 0 0 0|0 0 0 0|0 0 0 0| Bits
; |1 - - -|- - - -| Bus Number | Device |Func |Reg |- -| Definition
; |1 0 0 0|0 0 0 0|0 0 0 0 0 0 0 0|1 1 0 0 0|0 1 0|0 0 0 0 0 0|0 0| Bits
; | 8 | 0 | 0 0 | 24 | 2 | | 0 | Decimal
; | 8 | 0 | 0 0 | C | 2 | | | Hex
; |_______________________________________________________________|
dtl_add equ 08000C288h ; DRAM Timing Low
dth_add equ 08000C28Ch ; DRAM Timing High
dcl_add equ 08000C290h ; DRAM Configuration Low
dch_add equ 08000C294h ; DRAM Configuration High
ddr_add equ 08000C298h ; DRAM Delay Line Register
;---------------------------------------------------------------------
; DRAM Timing Low Address
;---------------------------------------------------------------------
; CAS Latency(dtl)
tcl_data equ 0FFFFFFF8h ; CAS Latency (3bit)
tcl_2 equ 000000001h ; CAS 2
tcl_25 equ 000000005h ; CAS 2.5
tcl_3 equ 000000002h ; CAS 3
; Row Cycle Time(dtl)
trc_data equ 0FFFFFF0Fh ; Row Cycle Time (4bit)
trc_7 equ 000000000h ;
trc_8 equ 000000010h ;
trc_9 equ 000000020h ;
trc_10 equ 000000030h ;
trc_11 equ 000000040h ;
trc_12 equ 000000050h ;
trc_13 equ 000000060h ;
trc_14 equ 000000070h ;
trc_15 equ 000000080h ;
trc_16 equ 000000090h ;
trc_17 equ 0000000A0h ;
trc_18 equ 0000000B0h ;
trc_19 equ 0000000C0h ;
trc_20 equ 0000000D0h ;
trc_21 equ 0000000E0h ;
trc_22 equ 0000000F0h ;
; Row Refresh Cycle Time(dtl)
trfc_data equ 0FFFFF0FFh ; Row Refresh Cycle Time (4bit)
trfc_9 equ 000000000h ;
trfc_10 equ 000000100h ;
trfc_11 equ 000000200h ;
trfc_12 equ 000000300h ;
trfc_13 equ 000000400h ;
trfc_14 equ 000000500h ;
trfc_15 equ 000000600h ;
trfc_16 equ 000000700h ;
trfc_17 equ 000000800h ;
trfc_18 equ 000000900h ;
trfc_19 equ 000000A00h ;
trfc_20 equ 000000B00h ;
trfc_21 equ 000000C00h ;
trfc_22 equ 000000D00h ;
trfc_23 equ 000000E00h ;
trfc_24 equ 000000F00h ;
; RAS to CAS Delay(dtl)
trcd_data equ 0FFFF8FFFh ; RAS to CAS Delay (3bit)
trcd_2 equ 000002000h ; 2 clock
trcd_3 equ 000003000h ; 3 clock
trcd_4 equ 000004000h ; 4 clock
trcd_5 equ 000005000h ; 5 clock
trcd_6 equ 000006000h ; 6 clock
; RAS to RAS Delay(dtl)
trrd_data equ 0FFF8FFFFh ; RAS to RAS Delay (3bit)
trrd_2 equ 000020000h ; 2 clock
trrd_3 equ 000030000h ; 3 clock
trrd_4 equ 000040000h ; 4 clock
; Min. RAS active time(dtl)
tras_data equ 0FF0FFFFFh ; Min. RAS active time (4bit)
tras_5 equ 000500000h ; 5 clock
tras_6 equ 000600000h ; 6 clock
tras_7 equ 000700000h ; 7 clock
tras_8 equ 000800000h ; 8 clock
tras_9 equ 000900000h ; 9 clock
tras_10 equ 000A00000h ; 10clock
tras_11 equ 000B00000h ; 11clock
tras_12 equ 000C00000h ; 12clock
tras_13 equ 000D00000h ; 13clock
tras_14 equ 000E00000h ; 14clock
tras_15 equ 000F00000h ; 15clock
; Row Precharge Time(dtl)
trp_data equ 0F8FFFFFFh ; Row Precharge Time (3bit)
trp_2 equ 002000000h ; 2 clock
trp_3 equ 003000000h ; 3 clock
trp_4 equ 004000000h ; 4 clock
trp_5 equ 005000000h ; 5 clock
trp_6 equ 006000000h ; 6 clock
; Write Recovery Time(dtl)
twr_data equ 0EFFFFFFFh ; Write Recovery Time (1bit)
twr_2 equ 000000000h ; 2 clock
twr_3 equ 010000000h ; 3 clock
;---------------------------------------------------------------------
; DRAM Timing High Address
;---------------------------------------------------------------------
; Write to read delay(dth)
twtr_data equ 0FFFFFFFEh ; Write to read delay (1bit)
twtr_1 equ 000000001h ; 1 clock
twtr_2 equ 000000002h ; 2 clock
; Read to write delay(dth)
trwt_data equ 0FFFFFF8Fh ; Read to write delay (3bit)
trwt_1 equ 000000000h ; 1 clock
trwt_2 equ 000000010h ; 2 clock
trwt_3 equ 000000020h ; 3 clock
trwt_4 equ 000000030h ; 4 clock
trwt_5 equ 000000040h ; 5 clock
trwt_6 equ 000000050h ; 6 clock
; Refresh Rate(dth)
tref_data equ 0FFFFE0FFh ; Refresh Rate (5bit)
tref_100_156 equ 000000000h ; 100MHz 15.6us
tref_133_156 equ 000000100h ; 133MHz 15.6us
tref_166_156 equ 000000200h ; 166MHz 15.6us
tref_200_156 equ 000000300h ; 200MHz 15.6us
tref_100_78 equ 000000800h ; 100MHz 7.8us
tref_133_78 equ 000000900h ; 133MHz 7.8us
tref_166_78 equ 000000A00h ; 166MHz 7.8us
tref_200_78 equ 000000B00h ; 200MHz 7.8us
tref_100_39 equ 000001000h ; 100MHz 3.9us
tref_133_39 equ 000001100h ; 133MHz 3.9us
tref_166_39 equ 000001200h ; 166MHz 3.9us
tref_200_39 equ 000001300h ; 200MHz 3.9us
; Write CAS latency(dth)
twcl_data equ 0FF8FFFFFh ; Write CAS latency (3bit)
twcl_1 equ 000000000h ; 1 clock
twcl_2 equ 000100000h ; 2 clock
;---------------------------------------------------------------------
; DRAM Configuration Low Address
;---------------------------------------------------------------------
; DLL Disabled(dcl)
dll_data equ 0FFFFFFFEh ; DLL disabled (1bit)
dll_enable equ 000000000h ; Enabled(default)
dll_disable equ 000000001h ; Disabled
; Dimm Drive Strength(dcl)
dds_data equ 0FFFFFFFDh ; Dimm Drive Strength (1bit)
dds_normal equ 000000000h ; (Default)
dds_weak equ 000000002h ; (Beware)
; Read/Write Qued Bypass(dcl)
rwqbp_data equ 0FFFF3FFFh ; Read/Write Qued Bypass (2bit)
rwqbp_2x equ 000000000h ; 2x
rwqbp_4x equ 000004000h ; 4x
rwqbp_8x equ 000008000h ; 8x
rwqbp_16x equ 00000C000h ; 16x
; Bypass Max(dcl)
bpm_data equ 0F1FFFFFFh ; Bypass Max (3bit)
bpm_0x equ 000000000h ; 0x (Disabled)
bpm_1x equ 002000000h ; 1x
bpm_2x equ 004000000h ; 2x
bpm_3x equ 006000000h ; 3x
bpm_4x equ 008000000h ; 4x
bpm_5x equ 00A000000h ; 5x
bpm_6x equ 00C000000h ; 6x
bpm_7x equ 00E000000h ; 7x
; Command Rate(dcl)
cr_data equ 0EFFFFFFFh ; Command Rate (1bit)
cr_1t equ 000000000h ; 1T
cr_2t equ 010000000h ; 2T
;---------------------------------------------------------------------
; DRAM Configuration High Address
;---------------------------------------------------------------------
; Maximum Async Latency(dch)
async_data equ 0FFFFFFF0h ; Maximum Async Latency (4bit)
async_0 equ 000000000h ; 0 ns
async_1 equ 000000001h ; 1 ns
async_2 equ 000000002h ; 2 ns
async_3 equ 000000003h ; 3 ns
async_4 equ 000000004h ; 4 ns
async_5 equ 000000005h ; 5 ns
async_6 equ 000000006h ; 6 ns
async_7 equ 000000007h ; 7 ns
async_8 equ 000000008h ; 8 ns
async_9 equ 000000009h ; 9 ns
async_10 equ 00000000Ah ; 10ns
async_11 equ 00000000Bh ; 11ns
async_12 equ 00000000Ch ; 12ns
async_13 equ 00000000Dh ; 13ns
async_14 equ 00000000Eh ; 14ns
async_15 equ 00000000Fh ; 15ns
; Read Preamble(dch)
rp_data equ 0FFFFF0FFh ; Read Preamble (4bit)
rp_20 equ 000000000h ; 2.0ns
rp_25 equ 000000100h ; 2.5ns
rp_30 equ 000000200h ; 3.0ns
rp_35 equ 000000300h ; 3.5ns
rp_40 equ 000000400h ; 4.0ns
rp_45 equ 000000500h ; 4.5ns
rp_50 equ 000000600h ; 5.0ns
rp_55 equ 000000700h ; 5.5ns
rp_60 equ 000000800h ; 6.0ns
rp_65 equ 000000900h ; 6.5ns
rp_70 equ 000000A00h ; 7.0ns
rp_75 equ 000000B00h ; 7.5ns
rp_80 equ 000000C00h ; 8.0ns
rp_85 equ 000000D00h ; 8.5ns
rp_90 equ 000000E00h ; 9.0ns
rp_95 equ 000000F00h ; 9.5ns
; Idle Cycle Limit(dch)
icl_data equ 0FFF8FFFFh ; Idle Cycle Limit (3bit)
icl_0 equ 000000000h ; 0 clock
icl_4 equ 000010000h ; 4 clock
icl_8 equ 000020000h ; 8 clock
icl_16 equ 000030000h ; 16clock
icl_32 equ 000040000h ; 32clock
icl_64 equ 000050000h ; 64clock
icl_128 equ 000060000h ; 128clock
icl_256 equ 000070000h ; 256clock
; Dynamic idle cycle counter enable(dch)
dicc_data equ 0FFF7FFFFh ; Dynamic idle cycle limit (1bit)
dicc_disable equ 000000000h ; disabled
dicc_enable equ 000080000h ; enabled
; Memory Clock Frequency(dch)
mcf_data equ 0FF8FFFFFh ; Memory Clock Frequency (3bit)
mcf_100 equ 000000000h ; 100MHz
mcf_133 equ 000200000h ; 133MHz
mcf_166 equ 000500000h ; 166MHz
mcf_200 equ 000700000h ; 200MHz (1:1)
;---------------------------------------------------------------------
; DRAM DQS Delay Line Register
;---------------------------------------------------------------------
; DQS Slew Value(ddr)
dqs_data equ 0FF00FFFFh ; Delay Line Adjust (8bit)
dqs_1 equ 000010000h ; 1
dqs_2 equ 000020000h ; 2
dqs_3 equ 000030000h ; 3
dqs_4 equ 000040000h ; 4
dqs_5 equ 000050000h ; 5
dqs_6 equ 000060000h ; 6
dqs_7 equ 000070000h ; 7
dqs_8 equ 000080000h ; 8
dqs_9 equ 000090000h ; 9
dqs_10 equ 0000A0000h ; 10
dqs_255 equ 000FF0000h ; 255
; DQS Slew Control(ddr)
dqsc_data equ 0FCFFFFFFh ; Adjust DQS (1bit) & (1bit)
dqsc_slow equ 001000000h ; Slower DQS
dqsc_fast equ 002000000h ; Faster DQS
;---------------------------------------------------------------------
; Sub Routine
;---------------------------------------------------------------------
ORG 100h
SAVE1 PROC NEAR ; Save all register that will be affected by our code
push eax
push ebx
push edx
pushfd
ret
SAVE1 ENDP
SENDER PROC NEAR ; Active communication with address
mov dx,address
out dx,eax
ret
SENDER ENDP
RECEIVER PROC NEAR ; Comunicate with the address & receive the data
mov dx,address
out dx,eax
mov dx,data
in eax,dx
ret
RECEIVER ENDP
TUNER1 PROC NEAR ; Sending new data from ebx stack
xchg eax,ebx
out dx,eax
xchg eax,ebx
ret
TUNER1 ENDP
TUNER2 PROC NEAR ; Increase data (OR)
or eax,ebx
out dx,eax
ret
TUNER2 ENDP
TUNER3 PROC NEAR ; Decrease data (AND)
and eax,ebx
out dx,eax
ret
TUNER3 ENDP
RETURN1 PROC NEAR ; Restore register contents and return far to system
popfd
pop edx
pop ebx
pop eax
retf
RETURN1 ENDP
RETURN2 PROC NEAR ; Restore register contents and return to SATA bios
popfd
pop edx
pop ebx
pop eax
retf
RETURN2 ENDP
;---------------------------------------------------------------------
; Main Routine
;---------------------------------------------------------------------
INIT PROC NEAR
; save all register that will be affected by our code
call SAVE1
; trc = 13
mov eax,dtl_add
mov ebx,trc_13
call RECEIVER
and eax,trc_data
call TUNER2
; trfc = 15
mov eax,dtl_add
mov ebx,trfc_15
call RECEIVER
and eax,trfc_data
call TUNER2
; END Patch back to system bios or SATA jump (RETURN1 = System ; RETURN2 = SATA jump)
call RETURN2
INIT ENDP
ORG 200h
CSEG ENDS
END
;---------------------------------------------------------------------
; tictac A64 Bios Tweaker Rev 001 Alpha
;---------------------------------------------------------------------
AN8 Ultra : nForce4 Ultra + Silent OTES Heatpipe + 7.1 Audio (Max Vdimm 3.55V
is that a good solution? it s stable enough that motherboard? :p:
that was the board i was going to get however it was unavailable so i got the sli board and currently hold all 3 records for an abit overclock on them . stable enough for you?Quote:
Originally Posted by blueangelman
figured id make a note of this for everyone.
ddrv undervolt by .05 so in order to run tccd at 3.0 volts set vddr to 3.05 and vtt to 1.5v
TicTac i think that Data Drive Stregth in DFI bios set the Memory DQ Drive Strength field in DRAM Configuration High Address (bits 13-14).Quote:
Originally Posted by tictac
I suggest you to take into account all possible combinations of the refresh cycle in your tweaker. About Tref i think the bits in the Refresh Rate field of the DRAM Timing High Register are encoded in this way:
Bits 12-11 are the refresh cycle in us:
00 -> 15.6 us
01 -> 7.8 us
10 - > 3.9 us
11 -> 1.95 us
Bits 10-8 are the MemFreq where the refresh cycle selected in Bits 12-11 is given. These Bits are encoded like the DRAM MEMCLK Frequency field in the DRAM Configuration High Register:
000b = 100 MHz
001b = 120 Mhz
010b = 133 MHz
011b = 140 Mhz
100b = 150 Mhz
101b = 166 MHz
110b = 180 Mhz
111b = 200 MHz
However on the Abit Board you can select 216, 233 and 250 Ram Freq (through the bit 30 of the DRAM Configuration High Register i think), so we have:
000b = 100 MHz
001b = 216 Mhz
010b = 133 MHz
011b = 233 Mhz
100b = 250 Mhz
101b = 166 MHz
110b = 180 Mhz
111b = 200 MHz
anyone live near rhode island that wants to temporarily donate a venice for me to test to confirm that its a cpu microcode issue as to why 1 t isnt working for them? should have mushkin utt redline results soon waiting to borrow it off a friend.
What would that mean? That the board will always have issues with 1T & Venice or would an update to the CPUs or BIOS be needed? I really wanted that combo. :(Quote:
Originally Posted by chew*
Some ppl do have issues with 1T & Venice (like me... :() and the latest bios (1.5) doesn´t help at all...
well it appears i am one of the few people that has high fsb/ w 1t command rate without issues. It would also appear that i am one of the few that is using a clawhammer. That would mean that A. everyone has a cruddy venice or sandy which i doubt B. everyone has a bad board and mine is just cherry which i also doubt or C. the cpu microcode in the bios isn't optimized for those cpu's yet.Quote:
Originally Posted by Psyche911
Don´t get me wrong... i love this motherboard, and i know Abit will do it´s jog right, it´s just a matter of time. Chew* what are your temps?
damn i have a week 17 venice and a Storm G5 waiting at home,but I have to be the family chauffer today. DAMN IT!!!! O yea and new AN8 SLI hoping this will resolve the 1T issue. Good thing Newegg has a good return policy
is this kind of undervolting considered severe or acceptable or normal?Quote:
Originally Posted by chew*
inaccurate at best abit eq says 117f on average. Mind you i have a asetek waterchill pro and i run this cpu at 2.4 gig at default volts for 24/7 use. there is no way a asetek 3x120 radiator setup with fans on high is running at those temps.Quote:
Originally Posted by ukveld
kinda normal considering if you do a 3.3v rail mod you need 3.4-3.5v for the memory to see 3.3vQuote:
Originally Posted by situman
@chew*
you can update microcode using cbrom xxxxx.bin /cpucode cpucode.bin
take it from latest DFI nF4 615 BIOS
chew - depends on the mod.
a .05v undervolt on load is acceptable when 3.3=vdimm, but any more than that and there are problems.
tccd performance versus bh-5 on an8
tccd @ 300mhz timings 2.5-9-14-4-2-6-3-2-2-3-1t
bh-5 @ 240mhz timings 2-8-12-2-2-5-2-2-1-1-1t
clock speed of cpu is 2400mhz in both tests. I used this as an average overclock of what most people will see as a 100% stable overclock.
tccd
http://members.cox.net/italygirl25/t...comparison.bmp
bh-5
http://members.cox.net/italygirl25/b...comparison.bmp
as you can see the tccd manages to barely edge out the bh-5 in all tests but the performance difference is minimal. the choice is obvious for those with a weak memory controller and those already having bh-5 i wouldnt suggest going out and buying tccd.