Quote:
Originally Posted by MAS
I thought those were just 65nm A64 and not K8L :confused:
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Quote:
Originally Posted by MAS
I thought those were just 65nm A64 and not K8L :confused:
any info if i coul get an altair based cpu for around U$550~U$700? in q3/2007 (sorry 4 my bad english)
ummm......you will need a Crystal Ball to answer that :D
I think your all full of :banana::banana::banana::banana:.
No one knows how the K8L will perform. So unless you're a x86 cpu engineer sit down and shut the fruck up.
Please don't compare OCed to stock either.. You can't compare the two. You also have no idea how k8L 65nm process is? How can you make such wild claims that Intel 65nm is so much holier then thou. Their sure is a lot of insecurity on this forum its just a constant e-penis orgy.
I will admit I am a fan boy, been using AMD for a long time I never really had any problems and for a long time they were better then Intel, so I stuck with them. Plus I really hated the Netburst architecture.
Also doesn't AMD use the SOI process as well where as Intel doesn't?
Its only 3 months off from q1 so sit tight don't get your panties in a bunch and enjoy the current product that you own.
Also guys calm down, its not like enthusiasts matter that much. AMD is now happy because of Dell, Dell pushes crap load of PC's to people. Most of them don't know or don't care what setup gives them an extra second in the 1 mil superpi bench.
I remember reading a little snipit of why there is no K9 its because K9 stands for Dog.. Would you like your flagship product be named dog..
http://xs208.xs.to/xs208/06442/CONROE-L-NOR.JPG 512kb Stock
http://forum.pcstats.com/showthread.php?t=37608 VS 4mb Stock
http://xs208.xs.to/xs208/06442/266-pi1m.JPG VS 4mb 3.1ghz
This proves conroe is cache dependent and since this is a single threated benchmark the difference between having 2 cores and one in Super pi doesn't exist. A single core AMD scores the same in super PI just as a dual core does because only one core is used so this supports my statment super pi and conroe are made for eachother. With out the cache conroe would be no better then K8's arc wise. The rest is just a gimmic. Its real performance comes from having a insane amount of cache. In the real world it means nothing why AMD's act the same as conroes in performance because most can't tell or see the difference. Conroe was made to bench and its performance doesn't exist in the real world like its hyped in benchmarks because the cache is the main reason for such high scores in super pi but isn't reflected in every benchmark for a reason. Its also not reflected in the real world because most programs will not use all of the cache in the same way the benches do it was made for. In the real world the benches just don't add up for standard use as a system your just not going to see it in everyday things you do. Specially because of the FSB limit.
K8L may use this in a similar way to get more performance by loading stuff way before its calculated with the help of L3 like conroe's large cache size K8L may feel much faster because it uses this trick to make itself feel faster by processing something far ahead of time wile its already loaded into cache afterwords. The more cache you have at this level usouly makes a big difference in performance but not the case with AMD in the past with K8's. Yet I beleave the cache may effect K8L more like Conroe does since its similar with large sizes of cache. Having L3 should make it feel much faster yet I could be wrong because it could be similar to K8's in that way and cache may not matter at all. But hyper transport would accelerate this effect it may help. If intel could do hyper transport then AMD would be in trouble. But since CSI will never come out before HT4 they don't have a chance in hell with FSB agenst K8L until 2009 with CSI-2. By then K11 will be out on 45nm going to 32nm with SOI-4 and 5.
AMD uses Victim Cache policy, it doesn't prefetch data like Conroe's cache.
Seems like K8L's L3 cache won't do it too, but because it wil be shared amog all CPUs, it will be a great help in multi-threaded applications.
btw, Opteron 2222s are sampling for production @ 65nm. they are 3.0ghz parts. :)
dave
Please tell us more..about everything Dave:D
i doubt that dave could tell us much more being under nda like he is
Quote:
Originally Posted by doompc
AKA BOTH AMD AND INTEL USE VICTIM CACHE AND THEY BOTH USE PREFETCHING. To assume AMD doesn't is just plan retarded :stick:Quote:
Originally Posted by Wiki
wish I could....but early signs are good.Quote:
Originally Posted by red
dave
Quote:
Originally Posted by Serge84
ROFLMAO!!! Those are some very entertaining theories! :clap:
It's called shared cache moron. Conroe can used caches from both cores in single threaded apps.Quote:
Originally Posted by Serge84
So what if Conroe uses cache to beat AMD? It's the end performance that matters.
Americans used better weaponry to defeat Iraq - although I bet if you limit them to fist fights the Iraqis will fare a lot better. :rolleyes: ;)
And FYI, real world Conroe performance is a heck of a lot better than what AMD can muster atm. I really don't know who you're trying to kid here. I'm aware it's the AMD forums but I suggest you go back to the [H] n00bs with your wingman duby229 if you wish to sprout such fanboy BS.
You already got owned enough in the FX 55 vs E6300 thread and now you come back for more? Incredible.
K8's L2 cache doesn't prefetch data because it is a Victim Cache.
If a L2 cache miss occours data is loaded from RAM to L1 cache, so some data from cache L1 is evicted to L2.
L1 cache can prefetch data from L2.
Conroe's L2 cache cannot be Victim Cache cause it is Inclusive (includes a copy os L1 data).
Conroe's L2 cache can prefetch data from RAM!
dave_graham, AMD stated that 65nm K8 will be <= 2.6GHz
http://www.planet3dnow.de/cgi-bin/ne...?id=1159444771
If they are making 3GHz 65nm K8s, 65nm process is going very well.
Don't be too harsh on Serge or the Ghost, they are die hard AMD fans. Next thing you know, they will dream up some good theories and say 90nm A64X2 runs faster than 65nm Conroe.Quote:
Originally Posted by Epsilon84
BTW, still no benchies for 65nm A64X2s? :o
As doompc mentioned, the shared, big cache on Core2 is much more valuable than a normal shared cache of the same size.
Normally a big cache is almost useless for reading of new data. But Core2's L2 cache has speculative prefetch, which means it can get cache lines before confirming they are actually what is needed. If they turn out wrong it can discard them. The K8 cannot do this and I didn't hear anything that would indicate that this will happen. As a result, a K8 cache can only fetch lines very late after the CPU can proof that no further instructions will change the requirement for that particular cache line.
Do you have a degree in logic and we don't know ? :slap:Quote:
Originally Posted by uOpt
wtf are u smoking ?!Quote:
Normally a big cache is almost useless for reading of new data.
It boils down to Intel's prefetcher being more advanced than in the K8.This is due to the P4 , which had a prefetcher far better than anything else ( we might say it needed it with such lentghty pipelines ).Prescott stepped up the level and Conroe simply builds on that.Quote:
But Core2's L2 cache has speculative prefetch, which means it can get cache lines before confirming they are actually what is needed. If they turn out wrong it can discard them. The K8 cannot do this and I didn't hear anything that would indicate that this will happen. As a result, a K8 cache can only fetch lines very late after the CPU can proof that no further instructions will change the requirement for that particular cache line.
Whats with the sudden influx of newbies with these condescending attitudes? Is it really so hard to simply have a thread without all these :banana::banana::banana::banana: fits? There is possibly seven pages total of people flame baiting and biting at it.
I got a feeling here soon the Ban Hammer of Fuggality is gonna get brought down against some newblet heads, and an otherwise thread of decent information is going to get closed.
Incase you didn't get the memo.
And Dave, do keep us updated. Its greatly appreciated. Good info.
:clap:Quote:
Originally Posted by Reznik Akime
This msut be one of the worst threads in all XS, it's a shame that people cant give eachother anything because they are all the uber know-it-alls.
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roger that.Quote:
Originally Posted by nn_step
so...let me get this straight. Rev.G will use SiGe?
which Stepping of Rev G?
Because the first few No
a Couple later ones Yes
Why call a bloke a moron, just because you disagree with him.Quote:
Originally Posted by Epsilon84
I think your post shows your level of maturity.
Grow up please.
Sometimes you have to speak the truth...being polite when arguing with an idiot is making him an unnecessary favour.
The favour is to yourself. If you are not polite, it reflects poorly on both yourself and your message. Rudeness is often an attempt to add the illusion of strength to a weak message, and people tend to treat it as such. If you are speaking the truth, it is best to be civil.Quote:
Originally Posted by savantu
I know this post is off-topic, but in this thread (and others) it seems relevant.
Hmm, looks like K8 does prefetch data from the RAM:
http://www.cpuid.com/reviews/K8/index.phpQuote:
The K8 also includes an hardware prefetch logic, that allows to get data from memory to the L2 cache during the the memory bus idle time.
Not prefetching is just stupid. Simple prefetching is rediculously easy to implement, just like a victim cache. It's large gains for very little work and cost (die size, etc). Therefore, I call bogus on the "no prefetching" statement.
Something I started wondering recently. After watching what nvidia pulled off with their G80, who's to say AMD isnt' doing the same thing. Is there any reputable evidence that says all that 65nm is, is a shrink with no improvements?
disclamer:
(they're may be, i don't know)
Yes, AMD themselves have said time and time again that the new core™ is to debut in the second half of the next year.Quote:
Originally Posted by flippin_waffles
This thread just made me think of something: We still haven't seen any rev G CPUs, despite them being out in just a few days! What are the chances that AMD is as tight with rev H as rev G? Could be a long wait...
It's really very unusual for a product to be kept under such secrecy as rev G has been. It's kind of strange, as the CPUs really don't seem to be more than die shrinks.
Quote:
Originally Posted by Mikael
That's what I mean. They seem to be, but i wasn't aware of any concrete evidence that says that is all they are. I never realized that AMD themselves iterated this, so thanx!
The avaliblity of ES samples depends alot on whos gonna use them.
If 65nm K8s can be plugged into a MB without a BIOS update and all VRM is fine. Then there is no need for AMD to make alot of ES samples and distribute to OEMs and MB makers. Another option is also that 65nm K8s aint ready yet, or just become ready and is very thight with any form of avaliblity.
Actually, I think AMD started mass production several months back. I think I read it in an interview with an AMD employee.Quote:
Originally Posted by Shintai
There have been 65nm CPUs kickng around for AGES..fact. S7 had a couple on 939 to test some early ideas for AMD (before AM2)
AFAIK, yeilds are good on 65nm coz they`ve had a while to get everything just the way they want it. I reckon a few memory controller tweaks to test ideas for K8L.
If people are banding about ideas on other reasons for 65nm being so quiet because its more than just a die-shrink, I have my own conspiracy theory that no-one wants to hear. ;)
If its just a die-shrink, I agree with the "ES arent needed en masse" idea
i want to add something about the X4. I call the AMD quad core X4 because K8L is a name from intel, and i prefer the AMD real name, misteriously don't exist.
I called the AMD press service and the chip is called Quad core. X4 to make more short.
I want to add some informations about X4.
I have seen that the L3 is half exlusive. ( and half inclusive ) with L1D/I ( don't remember it was L1D or L1I :cry: )
There is two revision of X4. A0 still have some bugs with decoders, and A1 is perfect ( theinquirer )
X4 have 4 complexe decoders. ( K8 3 simple 1 complexe )
The whole chip have been revised.
To people who want know what about Quad Fx platforme ( 4x4 ) CPU are not 65nm, i will answer that there is no brisbane with 1024ko of L2. Windsor 90nm, the core taked for 4x4 is 1024ko.
3.5ghz overclock is possible in deed. I want to remerber you the 130nm=>90nm transition. AMD go 2.2ghz K8 to 3Ghz today Fx74.
The 90nm san diego was the revision witch was the one who give the overclock easy with AMD K8.
Actual 90nm is SOI DSL. The 65nm is SiGe.
SiGe is used for hyperfrequency hardware. AMD tell us that the 65nm will give 42% improvement about the transistors.
Imagine 42% more that 2.8ghz-3ghz => 3.9ghz-4.26ghz ^^
I don't really think that AMD will do that incredible achievement. But i realy think that brisbane will clock easy @3.5ghz-3.6ghz like conroe.
I want to remember that Brisbane is not a die shrink. Brisbane can do 0.5 multiplier. The 5 dec 06 AMD will release some models on 65nm.
I want to spot light on the P rating about the Brisbane.
4400+ 65nm : 2.3ghz 512ko*2
4400+ 90nm : 2.2ghz 1024ko*2
4800+ 65nm : 2.5ghz 512ko*2
4800+ 90nm : 2.4ghz 1024ko*2
+100mhz = cut 512ko
4200+ 90nm : 2.2ghz 512ko*2
4000+ 65nm : 2.1ghz 512ko*2
The 4000+ have 100mhz less and loose 200+
in single core 512ko/1024ko are 300+
in dual core 90nm 512ko/1024ko are 200+
in dual core 65nm 512ko/1024ko is +100mhz
These P ratings are very curious ...
Next i don't have any information about K10, but i speculate that AMD will use to make his K10. I recomand every body of you to see very attentively Fusion and GPGPU. I think i have found the secret of the reverse hyper threading.
X4 is better core.
K10 is reverse hyperthreading with more cores and a new internal bus.
i may have too said ... :woot:
Excuse my very strange language :D
1) ALL K8 have 3 complex Decoders, only conroe has 1 Complex and 3 simple
2) can be exclusive or inclusive, it would be inefficient to do both
3) Half multis and half dividers are going to seriously improve AMD memory performance.
4) expanded Divider options will allow even higher memory Ram (yes of I am speaking of a divider of 2 :D )
5) increasing L1 bandwidth will allow AMD to be the first Company to fetch 32 byte blocks (double that of Conroe) Meaning that its issue rate is far less constrained than Intel's in theory allowing far greater performance.
Sure in Theory Conroe can under Ideal circumstances is able to execute 5 instructions, but only if the instructions are less than 4bytes large on average
i may confused :p:Quote:
Originally Posted by nn_step
Scienta's Blog :Quote:
2) can be exclusive or inclusive, it would be inefficient to do both
AMD's L3 is also more complex than I had thought. I had expected the L3 to be exclusive but AMD has apparently decided to make it more complex. They use it exclusively with data but can use it inclusively with instructions. This is a big improvement and would tend to negate most of Intel's advantage with inclusive cache and its advantage with the shared L2. However, this multi-mode function allows AMD to retain its current cache size flexibility. It would be able to change the size of both L2 and L3 without a severe penalty in performance. Intel does not have this flexibility. Further, Intel's use of shared L2 leaves the processor vulnerable to cache thrashing where one thread pushes instructions out of the L2 only to have its own instructions pushed out by the first thread in a cpu clock wasting tug of war.
i think his right
you're rightQuote:
3) Half multis and half dividers are going to seriously improve AMD memory performance.
Explain a bit more please :p:Quote:
4) expanded Divider options will allow even higher memory Ram (yes of I am speaking of a divider of 2 :D )
Don't think Brisbane have 32byte fetch :stick:Quote:
5) increasing L1 bandwidth will allow AMD to be the first Company to fetch 32 byte blocks (double that of Conroe) Meaning that its issue rate is far less constrained than Intel's in theory allowing far greater performance.
Sure in Theory Conroe can under Ideal circumstances is able to execute 5 instructions, but only if the instructions are less than 4bytes large on average
Brisbane has 128bit (or 16Byte) fetch but the logic for supporting 32byte fetch is includedQuote:
Originally Posted by madcho
interesting ;)Quote:
Originally Posted by nn_step
32Byte instruction fetch will only be possible in K8L, cause is has 256bit L1 cache bus.
K8L decoders are faster than K8's, the 3 of them can decode complex instructions in 1 cicle (2 cicles in K8).
Conroe has 1 slow/complex and 3 fast/simple decoders, but the fast decoders can handle SSE instructions.
Can anyone confirm if rev G ou H have half memory dividers ?
This would finally allow setting the exact clock frequency for almost every cpu/ram frequency.
X4 have four decoders, i saw it on the die shot. It's very clear, we can see 4. :toast:Quote:
Originally Posted by doompc
I think the memory controller will be a bit better in the new 65nm k8 since Amd seems to improve the mem controller in each revision:D
Im waiting for 65nm
And for k10 Barcelona
It seems very promising:toast:
geez somebody leak some ES already! AMD is killing me with this silent treatment. It's like seeing tumbleweed rolling through here the past couple months..
Those 2 CPUs (ADV4_00) were low power 90nm models...Quote:
Originally Posted by K404
you think so? why hold an NDA over details for just that? Low-power 90nm would be like the EE chips we see now.... nothing special, just take a good stepping and knock the voltage down. :)
There are two memory controller ont the X4 :stick: we can see it on the die shot :woot:Quote:
Originally Posted by Teroedni
two dual channel Memory controllers with support for DDR2 and DDR3Quote:
Originally Posted by madcho
K404,
You didn't happen to mean this thread?
Does it have 2 64 bit memory controllers that support both DDR2 and DDR3 or 1 dual channel DDR2 and 1 dual channel DDR3 controller?
The answer will surprise youQuote:
Originally Posted by doompc
do we know what socket this is going to be on..?? AM2, SoF??
X4 ? AM2 for start and AM2+ ( AM2 & HT3 ) next AM3 , ... :stick:Quote:
Originally Posted by Mankz_91
so....surprise usQuote:
Originally Posted by nn_step
X4 AM2/AM2+ will have memcontroller supporting both dd2 and ddr3, but with locked ddr3 part.Quote:
Originally Posted by Qkjhfhaiguihfma
ddr3 support will be unlocked for 939-pin (socket AM3)
form-factor
MAS,
The question was whether K8L has two 64bit or one 128bit memctrl.
or perhaps two 128bit memory controllers
two 128bits controller, but one is locked.
on AM2 the controller DDR3 is locked.
on AM3 the controller DDR2 is locked.
very easy to understand :)
lol, actually no, I hate labeled socks.Quote:
Originally Posted by LOE
Only my avatar features Wagner, I prefer my garments without labels.
edit:128bit...Quote:
Originally Posted by nn_step
You mean dual 64bit memctrls for DDR2 and another pair of 64bit'ers for DDR3?
A "true" 128bit ctrl would rule out SC memory bus and enforce consumer to use a minimum of 2 memory sticks. In other words, K8L would be stuck on dual channel. But in the end, I guess SC would seriously constrict K8L, thus there would be no point in SC configs anymore.
AMD's current A64 controllers are 128 bit and have been for some time but you can still run them in single channel mode if need be.
:stick: :stick:
This whole thread is :banana: :banana: :banana: :banana:
How can anyone know WTF it's gonna do till it get's here:nono:
"All is congecture until proven" (me)
TY!
Two 64bit MCs co-operating providing a 128bit bus combined.Quote:
Originally Posted by mesyn191
Just like ATi R520/R580 features effectively a 256bit MC but in reality its eight parallel 32bit'ers.
Please excuse the rant.:slapass:
Long thread:eek:
TY
you don't have to apologize when you're right ;)Quote:
Originally Posted by VaCreeper
Well there are ES procs available. Been trying to get my mitts on a set even though I expect to be NDA'd up the yin-yang once I have em.
Only thing I can see wrong with quad core in servers is that 4x cores on a DC 800mhz DDR2 memsys = problems for mem heavy tasks. Ideally I'd like the option of dual core K8L's so they can keep themselves fed data under the memory loads that I see at my work. But then again chip design and testing is not the average load for the home user here ;)
AM3 is 940-pins btw. Its the same as AM2 and AM2+. All future chips are backwords compattible even AM3 chips to AM2+ to AM2. But not the other way around.Quote:
Originally Posted by MAS
Are you referring to ES QuadCore called K10/K8L (rev H) or to ES K8/Brisbane (rev G) :confused:Quote:
Originally Posted by Demoulous
AM3 would have to be 939 pins, if it was 940 pins, anyone could shove an AM2 CPU in an AM3 board and blow something up. Being 939 pins, an AM3 CPU can fit into an AM2 socket, but an AM2 CPU cannot fit into a AM3 socket.Quote:
Originally Posted by Serge84
an am2 cpu cannot work in an am3 socket, as the voltage regulation is different. am3 can work with am2 though...Quote:
Originally Posted by Serge84
So......Does anyone know the exact release day yet????
Yes, however they will not tell you
Read again. Thats exactly what I said. All future chips are backwords compatible but not the other way around meaning no AM2 chip will work in a AM3 setup. :slap: :stick:Quote:
Originally Posted by cky2k6
Mind if I ask what pic? Link?Quote:
Originally Posted by madcho
The proverbial "4th block" isn't actually a decoder.
For example if we examine the freak AMD prototype ("freak prototype" on the left, real K8L die @low res on the right) caught floating around sometime ago we can spot quite K8-like instruction engine.
3 parallel complex decoders... But, the prototype ofcourse isn't K8L.
Anyone happen to have bumped into some high(er) res K8L die shots?
Now you broke all the diehard fanbois dreams :(
But ye, 2 eggs became 5 chickens with those decoders...
I propose you to see this hi res X4 die shot :
http://img314.imageshack.us/img314/6...overlayfs3.jpg
ps: i found this one in higher res, but i don't found it sorry.
madcho,
That pic is too low-detail and heavily photoshopped to see anything...
:(
2xBarcelona FX-2P on 4x4 mobo plus 2x AMD Radeon X2800XTX Crossfire plus AMD Stream processor demonstration would be the best gift for amdfans before Christmas
Don't think that ATI will release R600 before february :nono:Quote:
Originally Posted by MAS
Radeon X2800 Series test results will be published from 20 to 30 of January? and the videocard itself will be avail. from the 1-st of Fab.
i believe it will be launched 7th of decemberQuote:
Originally Posted by nn_step
p.d. this is not real k8l the one they will release in december
True that is just a 65nm K8
But AMD may offer a press demonstration of the X4 in december. :toast:Quote:
Originally Posted by nn_step
see the topic nameQuote:
Originally Posted by madcho
Waiting.. Waiting....
meanwhile...
FX-74 instead of K8L on 4x4 mobo
http://pc.watch.impress.co.jp/docs/2...9/tawada_1.jpg
the first tests
You guys do realize that the quad CPU 3GHz K8 is quite competitive with the QX6700, right? This is quite surprising... looks like K8L will beat the QX6700 by a substantial margin to me.
Of course, it's 3GHz vs 2.66GHz though...
yep K8L in 4x4 will own any Quad core in multi-threaded applications, by the sheer advantage of having twice as many cores
I'm talking about single K8L vs single QX6700
Saying that Quad FX is competitive with QX6700 is like saying that Extreme Edition is competitive with FX. Sorry, but nearly twice the wattage and not even beating it is hardly competitive when the Pentium 965 actually won some and not that much hotter.
in few months there will be FX-76 3,2GHz model - it will be even a little faster than Xtreme kentQuote:
Originally Posted by Shadowmage
just now AMD doesn't have enough 3,2 GHz stable chips for sell
red, for people who are able to buy 4x4 system its high power consumption means nothing
If AMD can manage 3.2GHz in 4x4 and it edges ahead of QX6700, expect QX6800 to follow shortly (if not before). OTOH why not just OC QX6700 to 3.33GHz now? I can't wait to see FX74 overclocking results!Quote:
Originally Posted by MAS
Now this is getting interesting.
Math doesn't seem to be your friend.Quote:
Originally Posted by Shadowmage
By how much , in relative terms , does the 4x4 lose to QX6700 ?
Is that competitive ? Mind you , A64 never enjoyed such an average advantage over P4 , yet nobody called them competitive. :slap:
You can take a look here , if you don't like chinese.
http://xbitlabs.com/articles/cpu/dis...d-quad-fx.html
And , K8L will beat QX6700 simply by coming 1 year later , otherwise it would be a real shame.Have you ever considered the possibility that Intel will have something better , and on 45nm , by then ?
At launch K8L should be going up against some shrunk QC Conroes... QC K8L should easily beat that, now the new core that Intel is supposed to have available in 2008 or so will probably change things up again, but we've known this for a long time now and have been over this many times to boot...
AMD is pretty explicit that they don't have 2 memory controllers on die, just one that can operate in different ways.Quote:
Originally Posted by largon
http://www.amd.com/us-en/Processors/...5e9493,00.html
http://www.amd.com/us-en/assets/cont...cture_WP_2.pdf
The Hammer microarchitecture incorporates a dual-channel DDR DRAM
controller with a 128-bit interface capable of supporting up to eight DDR DIMMs (four per channel) as seen in the Hammer microarchitectural diagram in Figure 2.
http://www.amd.com/us-en/assets/cont...docs/31411.pdf
Up to four unbuffered DIMMs in a 128-bit configuration, or up to two unbuffered DIMMs in a 64-bit configuration
The controller supports 64-bit operation (72-bits including ECC) or 128-bit ganged operation (144- bits including ECC). When configured for 128-bits, the upper and lower chip-selects are logically equivalent signals to provide adequate buffering to drive four DIMMs. DIMMs must be populated in matched pairs when configured for 128-bit mode. Figure 2 illustrates the typical DIMM connections in a 128-bit system with ECC support.
pages 11, 15, 16
ummm Dude that is K8
I know, he was saying that if a memory controller can run 64 bit mode than its not a true 128 bit memory controller...
Quote:
Originally Posted by largon
umm that is called backwards compatibility, forcing users to USE Two sticks of memory isn't good business. However letting them pick between two sticks for more performance and one stick for budget is a good idea.