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Like I said. Duplicating all functionality to allow AVX on both halves simultaneously would be a waste of die space and power. IMO, it's better this way.Quote:
128-bit dedicated FMAC per core
-OR-
256-bit AVX shared between 2 cores
Mmmm....I agree, if that slides true, a new spepping for late year as it would appear the rumors were true, the part isn't up to snuff. So release slow parts just to get somthing out. To me that means less performance than what we originaly led to believe.Quote:
Originally Posted by XRL8
RussC
AMD didnt anybody LED to believe in any performance numbers as it didnt state any, nor even implied them.Quote:
To me that means less performance than what we originaly led to believe.
All AMD officialy said is "AM3+ is a platform for our new bulldozer based cpus which will have up to 8 cores".Thats it :).
Recently we found out AMD plans to price first 8 core BD at around 300$ mark, so it thinks its gonna compete with 2600k.However its not official and isnt even verified to be true.
It doesn't have to be a new stepping,would be normal for AMD to have a roadmap with higher clocked parts to counter faster SB parts Intel might release and SB-E.
but really, new BOX for top models look impressive. The nicest from all history. Nice BOX and golden treasure inside :). Love it. Want it :).
Do has anyone picture of BOX in higher resolution? Its adept at my new windows desktop.
I didn't say AMD led us, just a general "led". Im thinking the intial release performance now will be more dissapointing than exciting.Quote:
Originally Posted by XRL8
RussC
Actually this slide makes the point even better:Quote:
Originally Posted by Solus Corvus
http://img11.imageshack.us/img11/9345/bd003.th.jpg
Basically the FP unit can process 2 128-bit instructions per cycle, whether they are FMA, SSE, or AVX (yes, there are some 128-bit AVX instructions). But a 256-bit instruction requires the whole module.
A glass half full or half empty, what a dilemma for fanbois around the globe, LOL. :ROTF:Quote:
Originally Posted by RussC
From what I heard, Fusion sales exploded much more than they expected (they shipped 5 million Zacate/Ontario chips and are now sold out). So they decided to change to prioritizing GF's manufacturing capacity for Llano first (more profitable). And at the same time do a new stepping for BD anyway (increasing clocks).Quote:
Originally Posted by RussC
CnQ is probably disabled/not working yet, I don't doubt idle voltages will be very low if the idle clocks are to be taken as valid.Quote:
Originally Posted by mrcmtl
i will have blueberry intel cookies there that I eat up :rofl:Quote:
Originally Posted by FlanK3r
Buy an AMD 8 core cpu, get a FREE PENCIL CASE!
Thats a strange box, looks like a cookie/popcorn tin to me :D
Seems like everyone who buy Bulldozer will get candybox with it.
Wow i see my Thai language printed at the box
When you consider that few apps will take advantage of 256-bit AVX, why would you want lots of die space and power budget dedicated to 256-bit AVX? Especially in client applications.Quote:
Originally Posted by Solus Corvus
You'll see 256-bit AVX in some HPC apps, a few financial apps. Mostly they will be custom apps, not commercial apps.
128-bit AVX will be far more common because there is a greater likelihood of 128-bit pipes being filled. Today's 128-bit SSE is probably only partially filled on most cycles (when it is actually being utilized) so the thought that suddenly it can be filled with 256-bit on applications, especially on the consumer side, is a bit far-fetched.
90% of the processing that happens in most environments is integer today, not FP. That means a lot of empty cycles for the FP unit.
"Warranty subject to certain exceptions and waivers"
Seems reasonable.
Easy answer: I wouldn't, unless apps important to me use lots of 256-bit AVX.Quote:
Originally Posted by JF-AMD
How many apps important to me fit that description right now? Zero.
IMO, BD should have relatively similar power to SB in 256-bit AVX. But the flexibility of the FPU gives it significantly higher potential in traditional FP, SSE, 128-bit AVX, and FMAC. At least on paper.
I will buy lowest clocked 8 core anyway and overclock myself. Due to watercooling i think i can make up for the difference at lower initial cost. And if I dont get out the 4+ ghz at once i dont really care, but i want a bulli FAST :DQuote:
Originally Posted by RussC
anyway, to me it seems different with this slide: The first steppings are delayed (because of llano or whatever), but the second steppings to be released are not delayed, but just like on earlier slides.
That way they have lower lifetime, but
1.) the first steppings will be in store for 1 year (can be ordered by resellers for half a year, then shipping, then in shops.. At least a year) - not really unusual. Maybe they have to cease to make room for second step bulli, as it seems that production capacity is an issue, so dont compare that with intel..
2.) If the second stepping isnt delayed, it means there are no technical problems with performance or whatever, otherwise the second steppings chips would have been delayed also... But they arent...
Conclucion: All fine with the process and bulldozer...
iron BOX with CPU for me.....love...
http://www.youtube.com/watch?v=FQtmr...layer_embedded
he said: "I think, people will be very impressed about clock speeds"...
But clocks do not mean anything. People should have been impressed by Pentium 4 clocks and look what happened.
dont worry....,-)
I am not, just don't like when clocks are used for PR.Quote:
Originally Posted by FlanK3r