Originally Posted by OSKAR_WU
I think you know DRAM frequency we set in A64 register is " Upper limit " of DRAM speed ... A64 memory controller will automatically choose a smallest interger divider(>4) to generate the DRAM clock from Core Frequency , and the DRAM clock will not be faster than the uppder limit ... Using an oscilloscope and check all the multiplier from 4~12 with the same register setting in A64 ... What I got are 200/183/166/150/143/125/100 may be the upper limit of DRAM speed when you set correspoding register setting in A64 ... Here is the divider table I got after using an oscilloscope to check the possible upper limit of DRAM clock ... What I can not be sure is the exact frequency besides 200/166.67/133.34/100 ...
