AMD Tapes Out First "Bulldozer" Microprocessors.

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Originally Posted by LightSpeed

What is up with the 32nm manufacturing? I understand that Bulldozer is complete but these manufacturing delays would affect both Llano and bulldozer...

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Bingo. Of course they do. Dirk's "on track" statement does not rule out process impact on the BD timeline, given that the bulldozer launch window is still 12 months long. Put another way, a hypothetical slip from Q2 to Q4 2011 would still mean BD is "on track".

But more directly, look: it's Q3 2010. BD hasn't sampled yet, per Dirk. For a new microarchitecture, the biggest change since k7-->k8, it's going to be AT LEAST 12 months from first silicon to production shipments, and probably more like 18 months. Don't expect any BD products until some time in H2 2011 at the earliest, if it remains "on track", and even later if either design challenges surface or the process troubles remain relatively intractable.

the core has two simultaneous architectural states. software will see two threads.

if you could give me the definition of what the rest of the world considers a core that would be great.

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Originally Posted by JF-AMD

We don't run multiple threads on one core. It is one thread per core.

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I stand corrected. I was more concerned with his understanding of SMT being counterfactual. But apparently I don't properly understand CMT either.

So it is 4 alu and one FP half per core? And it can only execute one thread concurrently?

XBit's article should have used past tense: AMD Taped Out Bulldozer in Q2.
As for the core vs module debate,this thing has 2 full discrete cores inside an optimized super core or as a proper term is :module . Shared front end is a design feature for maximizing the utilization of the cores among other things.Each of the cores can run one thread at a time,so for 8 cores(4 modules) it's 8 threads and for server parts it's 16 threads per one CPU. Each core within a module is 4 way OoO and has an access to either 1 256bit FMAC capable FPU or in shared mode 1 128bit FMAC capable FPU. FMAC means that each of the 2 FPUs can do fused Multiply Add instr. per clock.

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Originally Posted by Solus Corvus

I stand corrected. I was more concerned with his understanding of SMT being counterfactual. But apparently I don't properly understand CMT either.

So it is 4 alu and one FP half per core? And it can only execute one thread concurrently?

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Each core can execute a single thread simultaneously. An 8 core die can execute 8 threads per cycle, a 16-core processor can execute 16 threads per cycle.

As I understand SMT, a 4 core die has 4 pipelines. If one thread stalls, another can take over those pipelines and continue. So, while you technically have 8 threads active, only 4 are running in any given cycle. SMT takes advantage of thread stalls to fill the pipelines with the "on deck" thread. This is why the throughput increase is 15-20% (for servers).

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Originally Posted by Chumbucket843

the core has two simultaneous architectural states. software will see two threads.

if you could give me the definition of what the rest of the world considers a core that would be great.

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Generally speaking, the industry tends to look at simultaneous integer units as the basis for what they call a "core". Obviously there is no hard and fast rule, but at hot chips next month, I am pretty sure that if you asked the attendees (including intel) they would concur that bulldozer is an 8-core die, not a 4-core die. And they are the people that will know.

So regardless of whatever we are calling cores/modules, the first bulldozer parts will operate on 8 threads per cycle?

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Originally Posted by JF-AMD

Each core can execute a single thread simultaneously. An 8 core die can execute 8 threads per cycle, a 16-core processor can execute 16 threads per cycle.

As I understand SMT, a 4 core die has 4 pipelines. If one thread stalls, another can take over those pipelines and continue. So, while you technically have 8 threads active, only 4 are running in any given cycle. SMT takes advantage of thread stalls to fill the pipelines with the "on deck" thread. This is why the throughput increase is 15-20% (for servers).

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That's not SMT ( simultaneous multithreading ), but SoeMT ( switch-on-event multithreading ) which is a derivate of coarse grain multithreading. The event is a stall in execution of a thread caused by a cache miss for example.

SMT offers more gains than SoeMT, but it is also much more complex.

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Originally Posted by FlanK3r

yes, i think (my meaning), launch will at Q2 2011

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More H2 2011 IMHO ...

"According to an unofficial source familiar with AMD’s server plans, the chipmaker intended to commence mass production of certain versions of its Bulldozer-based code-named Interlagos microprocessors with 12 or 16 cores already in the first half of 2011. Other versions of the chips, e.g. with reduced power consumption or increased performance, were planned to be produced in the second half of the year."

I hope they will really start mass production for certain versions in the first half of 2011.:)

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Originally Posted by Solus Corvus

So regardless of whatever we are calling cores/modules, the first bulldozer parts will operate on 8 threads per cycle?

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8 threads per die. Valencia (server) and Zambezi (client) will have a single die with 8 cores. Interlagos (server) will have 2 die for 16 total cores.

here we go again with terrace's ontrack argument again..........sigh

Advanced Micro Devices Inc. Q2 2010 Earnings Conference Call - Seeking Alpha

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Originally Posted by JF-AMD

8 threads per die. Valencia (server) and Zambezi (client) will have a single die with 8 cores. Interlagos (server) will have 2 die for 16 total cores.

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Thanks for the clarification. So it's 4 modules 8 cores and 8 threads? Where does CMT fit in this picture?

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Originally Posted by Solus Corvus

Thanks for the clarification. So it's 4 modules 8 cores and 8 threads? Where does CMT fit in this picture?

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CMT is an integral part of the module, allowing for 2 cores, in stead of one. It's the reason why you're confused because you're looking at the cores like they're "traditional" designs, but they're not. Pay attention to the exchange between JF-AMD and Chumbuckett above. Each module holds 2 cores, so 4-module design = 8 cores/8 threads; 8-module = 16 cores/16 threads.

We aren't using the phrase CMT. We are just talking about cores. Cores (in our world and most others' as well) = dedicated integer cores.

So in essence Zambezi and Valencia will be 8 core processors that can execute 8 threads simultaneously. Theoretically they could execute 32 INT instructions plus 8 FP or 4 AVX at the same time, based on the number of INT and FP units. Does that sound correct?

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Originally Posted by saaya

not bad... but knowing amd i wouldnt be surprised if bulldozer ends up competing with haswel :lol:
lets hope they manage to roll this out quickly and without any problems... the last 2 times they really reworked their architecture it was pretty ugly, and even a tweak aka deneb took a good while...

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Intel only knows how much technology they have stored up, but considering Intel has not slowed down its research efforts considering their R and D spending and has simply just slowed down the release of its products, regardless of how good BD is, Intel likely has something waiting to crush it.

Deneb wasn't even that good really. It basically something that caught up to core 2 quad in speed and even here it still slower clock for clock.

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Originally Posted by tajoh111

Intel only knows how much technology they have stored up, but considering Intel has not slowed down its research efforts considering their R and D spending and has simply just slowed down the release of its products, regardless of how good BD is, Intel likely has something waiting to crush it.

Deneb wasn't even that good really. It basically something that caught up to core 2 quad in speed and even here it still slower clock for clock.

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Dude, put down the pipe. The last 2 revisions were istanbul and magny cours. Both of which came out ahead of schedule and higher than expected perf and perf/w and perf/$.

Edit:

And case you choose to count desktop as the only architecture that matters, Thuban was also released with much higher clocks than expected and is trading blows with the competition.

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Originally Posted by flippin_waffles

Dude, put down the pipe. The last 2 revisions were istanbul and magny cours. Both of which came out ahead of schedule and higher than expected perf and perf/w and perf/$.

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Unfortunately for AMD some of the increase in perf/$ came at the expense of lowering the $. [ :( for AMD, :) for the consumer ]

I found it interesting during the last round of earning reports to see that AMD and nVIDIA had about the same gross margins, at 45% and 45.6% respectively. While Intel's came in at 67%. For whatever reasons you want to believe, clearly Intel is able to generate more profits from each chip when compared to AMD. I doubt BD will reverse that trend, but I certainly hope it gives AMD a chance to get closer to profit level parity.

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Originally Posted by sdsdv10

Unfortunately for AMD some of the increase in perf/$ came at the expense of lowering the $. [ :( for AMD, :) for the consumer ]

I found it interesting during the last round of earning reports to see that AMD and nVIDIA had about the same gross margins, at 45% and 45.6% respectively. While Intel's came in at 67%. For whatever reasons you want to believe, clearly Intel is able to generate more profits from each chip when compared to AMD. I doubt BD will reverse that trend, but I certainly hope it gives AMD a chance to get closer to profit level parity.

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Intel traditionally has had higher gross margins due to it's lead in manufacturing. Lower nodes = more chips per wafer = higher margins! :) Great for Intel, sucks for AMD. Hopefully with AMD spinning off GF and certain people investing in GF, that will change in the near future. :up:

Near future being years, I'd say. Sadly in this field, thats long, long time. :/

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Originally Posted by JF-AMD

We aren't using the phrase CMT. We are just talking about cores. Cores (in our world and most others' as well) = dedicated integer cores.

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ok well what is cmt then, it is being included with BD right? how does it fit?

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Originally Posted by Solus Corvus

Thanks for the clarification. So it's 4 modules 8 cores and 8 threads? Where does CMT fit in this picture?

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It's quite simple, CMT allows two cores to consume like 1.5 times (assuming same fab process) the die-space of one core, but gives 2 times the performance of a core. AFAIK, a Bulldozer module consumes 90% of a Deneb core. That's why AMD can fit 8 cores like they're nothing. My memory does not serve me too well, however, with regards to Bulldozer's size.

I want some Bulldozer love :yepp: . Gonna be helpful for encoding and virtualisation. I think encoding is slowly becoming a frequent use for computers among people.

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Originally Posted by blindbox

It's quite simple, CMT allows two cores to consume like 1.5 times (assuming same fab process) the die-space of one core, but gives 2 times the performance of a core. AFAIK, a Bulldozer module consumes 90% of a Deneb core. That's why AMD can fit 8 cores like they're nothing. My memory does not serve me too well, however, with regards to Bulldozer's size.

I want some Bulldozer love :yepp: . Gonna be helpful for encoding and virtualisation. I think encoding is slowly becoming a frequent use for computers among people.

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I was aware of the extra core for reduced die space but wasn't aware that was related to CMT - which apparently isn't the right term anymore anyway.

However they achieve it, it's good that they are bringing 8 thread capability to the table. I look forward to a threading monster if they can pull it off. But it also remains to be seen what the single thread performance, power consumption, clocking, etc is like.