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That is until Mike hooks up with some ln2 - if he hasn't already.Quote:
Originally Posted by Anvil
With the cascade I have on the way I should be able to go to ~-100C - http://www.xtremesystems.org/forums/...d.php?t=253872
ln2 used wisely (Mike is most experienced) goes much lower: -170 or better.
I'm sure he's got something prepared :)
Anyways, you gained 900pts by just tweaking and thats nothing to sneeze at.
I haven't compared your result to Mikes, I'll do that later, I expect you've both got some strengths and weaknesses.
GullLars,
Last run for today.
2R0 C300 9260 stripe size 16KB, test file deviates from the config, _only_ 1GB.
Thanks for the files Anvil. The original request i quoted was posted in this thread on the middle of page 2, i also posted comments in other threads linking to it, and on diskusjon in the benchmark thread (i think).
I haven't got my desktop connected yet since it doesn't have wireless, and i only have wireless internet access ATM, so i'll hang on to the files and look at them, and then make something in a few days. Having the data ready to crunch is nice, so just keep em coming if you guys have more times and available drives/arrays ;)
steve, that's quite brute, man you could've atleast said a few words, some of the things said refer to you, yet you don't seem to mind it, it just fly right near you, quite astonishing,
you will have to step out of that behavior of not dipping your hands into any conflicts, keeping everything smooth and nice,
or rather you are at a different class, you know how to behave, you know the lines and you never cross them,
i have never met anyone like that, that's quite insane.
i'm just struggling to figure that one out.
lars,
a bit off topic from your post, yet there's some interesting papers regarding some more deeper info on SSD's, 3 bit per cell, 2 bit MLC, error rates, general build, the papers are quite complex, yet they take the reader further on into the process, disclaimer: don't read unless you understand.
there is a thread at AT you might like to see, it's in the storage memory forum under 8kB page size on IMFT new 25nm flash?, there are some links there, you can go through even briefly and fish out some facts.
there is also this one, http://www.cyclicdesign.com/whitepap...n_NAND_ECC.pdf dealing with error rates and error correction,
it comes fit with the adoption of 25nm and 8kB pages in NAND technology, as the technology shrinks, the hurdles faced by engineers and research centers are much bigger, making 3BPC MLC a legitimate junction in the road map,
the hurdles are higher error rate due to tighter voltage differences through cell programming and bigger erase pages causing the NAND to drop endurance significantly.
with that coming the development of 100K P/E cycle MLC and 1M cycle SLC for strictly enterprise usage.
some interesting read feeling the mind with some new ideas!
there is also Micron's blog and release press sharing some info, and some nice links to youtube video's too.
there's more and more, so go read read and read :).
Onex, your rants are getting out of line. Every time I read one of your posts I struggle to understand what you are trying to say. I don’t know what you’re trying to say about Steve but you certainly got the 1st bit right. He is a fair person, polite, and (well) mannered. He helps people out and shares. How could you have beef about that? That is a rhetorical question by the way :up:
onex,
I'll have to agree with audienceofone here.
Remember that all of us are doing these activities in our leisure time.
A small note on the testing.
I've done my share of testing and it is very time consuming, especially when I do my own tests and then some variation of my own tests for the forum.
A few days/weeks later there is a new variation of the same test (I'm talking about iometer if anyone wonders), and then it's the same "work" over and over again.
If we could agree on some standard test config files it would make life a lot easier.
(I know we are in the middle of something new here, sort of uncharted territory but we need to agree on where we go from here)
Onex, I too agree with audienceofone and anvil here. I don't see why you would have a beef with Steve.
It's OK that you are trying to get more stuff to happen, but it can be hard to understand what you write, and some of it comes across as overly confrontational, and other parts almost political or philosophical in nature.
I have already read the material you refer to with exception of the Anandtech forum. I've also read all articles on Storagesearch on SSDs and related stuff (about 150 has been published i think), SNIAs papers, ONFI papers, some ECC and wear leveling and garbage collection papers, and other low-level architecture stuff. I follow the micron blog and are subscribed to their youtube channel ;)
If you haven't read it, i would suggest reading the IDF (intel developers forum) whitepaper on the effect of spare area on write amplification, and an IBM research paper on writing algorithms and more in SSDs (Anand used it as a source for his SSD anthology).
2 more tests
X25-E 2R0 on the 9211
One test is using SW raid, 4KB stripe size, the other one is defined in the MSM which gives 64KB stripe size. (hopefully they'll allow for other stripe sizes in future releases)
A note about my test using the C300s, although the testfile is 1GB the test is valid as the test is performed without using the controller cache. (DCD -> Disk Cache Disabled)
Disk cache disabled... Do you mean the cache on each of the C300s, or the RAID controller cache?
Disk cache disabled on the controller, I don't think it's possible to disable the caching on the SSDs.
i think it is disk cache.
cached i/o or direct i/o is how you set it between using cache or not on the controller....so that only leaves one possible explanation for "DISK cache enabled/disabled"
computurd
you may be right about the disk cache policy, it is however a bit more to it.
DIO = for reads all data is bypassing the controllers cache, except when read ahead is enabled, for writes all data bypasses the controllers cache except when WB is enabled
CIO = all data passes through the controllers cache including writes even when WT is enabled.
BTW, CIO is being deprecated.
Given this, one can do iometer read tests on the LSI using 1GB filesize as long as DIO is enabled, for writes WT must be enabled.
Link to LSI document
As for the disk cache policy, the setting does make an impact in some benchmarks (depends on the SSD), I haven't spent much time testing it though.
yes they also have an option in the MSM for running garbage collection manually on the drives in an array, but it is still grayed out....wonder when that will come through? :)
I havent noticed much difference on the disk cache..i have tested it in several configurations and never any noticeable difference.
one thing i have noticed is it seems that in always read ahead and DIO i get the best results as long as write thru is enabled. the latency with always read ahead is the same as well. from running the profiles that gullars gave me, there is no difference basically as long as write-thru is enabled the results are the same, but real world and loading tests always read ahead is better.
Non SSD discussion/rant but hey. Check out 3D video mapping on this site. http://www.urbanscreen.com/usc/category/projects
Well wicked. (Especially P.O.P & 555 Kubik.)
As for storage check out DiskMax. Nice programme. The MEM clean is quite good as well.
http://www.koshyjohn.com/software/diskmax.html
awesome guide, long read but well worth it!
Quote:
How could you have beef about that?
Quote:
I'll have to agree with audienceofone here.
just make some order in all of this,Quote:
Onex, I too agree with audienceofone and anvil here.
there's no "beef" with anyone really, there's not "bad" feeling, it is just something meant to wake people up,
there are things to be said, yet people would have to be aware at them otherwise it is just seems misplaced.
it is just the behavior at this forum, it is behavior of people, it is how people are used to behave and they take it normal,
when someone point it out, they just don't seem to understand what he\she is talking about and it is also seen through the nature of the comments.
as for that,Quote:
I have already read the material you refer to with exception of the Anandtech forum. I've also read all articles on Storagesearch on SSDs and related stuff (about 150 has been published i think), SNIAs papers, ONFI papers, some ECC and wear leveling and garbage collection papers, and other low-level architecture stuff. I follow the micron blog and are subscribed to their youtube channel
If you haven't read it, i would suggest reading the IDF (intel developers forum) whitepaper on the effect of spare area on write amplification, and an IBM research paper on writing algorithms and more in SSDs (Anand used it as a source for his SSD anthology).
i'll note, that these papers are not so easy to figure, one needs some background with mathematics, and has to study deeply in order to understand these papers coherently.
it is not enough to just skim through them or read them briefly, it is not enough either to get the general idea,
it demands a great deal of studying in order to figure them out properly and be able to cross between idea's and views lent through them, figure out things which are not written and so on, it also takes time and thinking.
but if you say you understand them, well, o.k ;).
Areca 1231ml-4g/5xAcard 9010 R0 results 4k stripe, 4K allocation attachedQuote:
Originally Posted by GullLars
I've done 2 years at a university studying chemistry before "dropping out" to study computer science instead, and in that time i did 2 semesters of calculus. I also majored(?) in mathematics, physics, and chemistry in grades 12 and 13 (would you call that high school or college? I'm not sure about the english term for grades 11-13). I may not understand everything in all the papers, but i understand the equations and what they describe, and also how they evolve.Quote:
Originally Posted by onex
If you were to compare the material and time i've "studied" SSDs (articles, architecture, working on data from benchmarking), it would likely compare to 2-3 courses in a university (at least the same effort on my part compared to the courses i actually took). Still, there's probably a lot i don't know, and i'd like to learn more (both SSDs and computer architecture and workings in general), which is one of the reasons i'm switching to computer science.
EDIT: looking forward to your results steve. I'm getting my gaming rigg / workstation hooked up to the net tomorrow, so then i'll likely be more active with benchmark data again. Looking forward to my 1900x1200 monitor after a couple of weeks on a 15" laptop with 1280x1024 :)
Areca 1231ml-4g/5xAcard 9010 R0 results 4k stripe, 64K allocation attached
curious to see if the 64K allocation shows a difference - I thought I saw a big increase in going from 4k to 64k allocation is pcmv HDD test.
ok so the last run for tonight - good night all.
SteveRo_9211-8i_8R0_Acard9010_8x2GB_4kstripe_4kallocation_980x_ no_oc_pcie100 attached
gullars,
i'm talking about being able to write a thesis about it, writing a research, if you as a person, understand what is being said, you can go forward with it.
if you don't exactly understand what is being said, you skim through the paper or read briefly through it, missing a lot of details that takes away the effect of the paper, takes away the ability to go on from there.
this is why it is extremely important to understand everything that is being said, and if anything is misunderstood, figuring it out at all cost.
that's the only way one can figure out things better.
when one figures out some very complex material, it gives him also better understanding in other fields, if you don't challenge yourself, if you don't push where you cannot understand, where it seems to hard to reach, you never go on properly.
you should query every question raised and every idea to it's end, every confusing acronym or unknown feature.
going through any material without fully understanding it, has very little value,
and it doesn't matter going alone, it doesn't matter having days of not figuring out things and just watching the news, and sometimes you have to think nights in order to figure a certain aspect of the hardware a graph, equation, constant or an analysis,
but then it is all over,
ones it is there, once it springs through your mind, it will stay there, and you understand it so well, you can actually hold it.
Mostly, the stuff in the papers i don't fully understand is the specifics of the photo lithography, low-level circutry (like connector, signal driving details, and transistor workings in detail), and how the ECC and redundant algorithms works in detail (how it calculates data). I'd say i've got a pretty good understanding of the higher level architecture and workings of SSDs, and do a real effort, like you say, to not let go off things i don't get right away in more in-depth papers. Edit: i think this reflects a bit in my long ONFI rant on the first page of this thread ;)
i personally dont know crap about the inner workings of them :) I just reap the rewards! (and abuse them mercilessly)
The data cable goes to the smallish plug and the power to the wider one. :)