LP JR P45-T2R, E8600, 550x8, 2x2GB Memory 1100MHz, Post 1 of 3
DFI LP JR P45-T2R, 10/30 BIOS
550x8, Memory 1100MHz
E8600
2x2GB OCZ PC2-9200 Flex II 1050MHz 5-5-5-18
SAPPHIRE 4870
OCZ Core SSD
Orange Slots Used For Memory
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Code:
CPU Feature Page
Thermal Management Control................Enabled
PPM(EIST) Mode............................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Execute Disable Bit.......................Enabled
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled
Main BIOS Page
Exist Setup Shutdown......................Mode 2
Shutdown after AC loss....................Enabled
AC Shutdown free..........................Enabled
O.C. Fail Retry Counter...................1
O.C. Fail CMOS Reload.....................Disabled
CPU Clock Ratio........................... 8x
CPU N/2 Ratio.............................Disabled
CPU Clock.................................550 MHz
Boot Up Clock.............................Auto
CPU Clock Amplitude....................... 800mV
CPU Clock0 Skew........................... 200ps
CPU Clock0 Skew........................... 0ps
DRAM Speed................................333/667
PCIE Clock................................100MHz
CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled
Voltage Setting Page
CPU VID Special Add.......................+175.0mV
DRAM Voltage Control......................1.957V
SB Core/CPU PLL Voltage...................1.55V
NB Core Voltage...........................1.3575
CPU VTT Voltage...........................1.18V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
CPU GTL 0/2 REF Volt......................0.67X
CPU GTL 1/3 REF Volt......................0.67X
North Bridge GTL REF Volt ................0.61X
FSB Vref.................................. 2A
DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Auto
Clock Setting Fine Delay..................Listed Below
Flex Memory Mode..........................Auto
CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................5
Precharge Delay (tRAS)....................15
All Precharge to Act......................5
REF to ACT Delay (tRFC)...................54
Performance Level.........................10
Read Delay Phase Adjust...................Listed Below
Write to PRE Delay (tWR)..................13
Rank Write to Read (tWTR).................10
ACT to ACT Delay (tRRD)...................3
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................3
ALL PRE to Refresh........................5
Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto
Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto
Clock Setting Fine Delay Page
DLL and RCOMP Settings .................By Menu
Ch1 DRAM Default Skew.....................Model 5
Ch2 DRAM Default Skew.....................Model 5
RCOMP Setting.............................Model 0
Fine Delay Step Degree....................70ps
Ch1 Clock Crossing Setting................Auto
DIMM 1 Clock fine delay...................Current 2476ps
DIMM 2 Clock fine delay...................Current 2476ps
Ch 1 Control0 fine delay..................Current 472ps
Ch 1 Control1 fine delay..................Current 472ps
Ch 1 Control2 fine delay..................Current 410ps
Ch 1 Control3 fine delay..................Current 394ps
Ch 1 Command fine delay...................Current 472ps
Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current 2492ps
DIMM 4 Clock fine delay...................Current 2428ps
Ch 2 Control0 fine delay..................Current 442ps
Ch 2 Control1 fine delay..................Current 442ps
Ch 2 Control2 fine delay..................Current 346ps
Ch 2 Control3 fine delay..................Current 332ps
Ch 2 Command fine delay...................Current 442ps
Ch1Ch2 CommonClock Setting................Auto
Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto
Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto
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LP JR P45-T2R, E8600, 550x8, 2x2GB Memory 1100MHz, Post 2 of 3
LP JR P45-T2R, E8600, 550x8, 2x2GB Memory 1100MHz, Post 3 of 3