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Theres only two ways to take for CPU design when it comes to metal gate AFAIK and ones for high performance/high TDP and the other is for low TDP/v.low standby TDP preference. Intel chose the high-k dielectric metal gate which means you get maximum clock speeds (makes for easy PR work too) and not much TDP advantage over what the basic node offers
Intel's 45nm offers both : high frequency and low power
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and AMD AFAIK chose low-k dielectric along with IBM, which is not made for high clocks at all but low power usage. SOI and other straining techniques combined can do better than having a metal gate BTW.
That's utter BS.SOI and metal gates address different factors of leakage , SOI is becoming less useful once you get to 65nm and lower.
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Around 1.5V is about the max possible a CPU MFG wants to retail at, and usually never above 1.4V nowadays. I wonder what the TDP is. Intel breaks the 130W barrier after 3GHz on Penryn at 1.216-1.248V, so what would 1.536V 3GHz quad get? Must be high but they're planning to retail 2.8GHz this year, so we'll see what they have to offer then.
Huh ? Where do you get this info ?