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QFTQuote:
Originally Posted by PallMall
also, Rev. H(K8L/Cities/Stars, etc....) is supposed to launch for s1207+ and sAM2+ is it not?, and for QuadFX, i sure hope they plan on releasing they're own chipset as well as a new one from nVidia, this 1 chipset/1 mobo crap ain't gonna fly...
He is back to the future now :),so leave him be :D.Quote:
Originally Posted by PallMall
@informal
"I think" isn't "I know". You really want to know what I think and why, or you just want to argue with me?
@oldblue
Right. For example, these features are boosting the performance of Core2:Quote:
Originally Posted by oldblue
http://realworldtech.com/page.cfm?Ne...06-07-2006#366Quote:
Pat specifically mentioned some performance numbers for memory disambiguation. According to him, moving loads ahead of stores can up to 20-25% on some workloads. Since he is not (by own his own admission) an architect, these numbers should come with a grain of salt. That being said, Pat is known for an impressive memory; he cited the precise number of transistors for two Intel CPUs off the top of his head. The 25% mark seems like a good upper bound, and the average is probably in the 15-20% range. He also gave some rough figures for how well macro-op fusion (i.e. combining x86 instructions) and micro-op fusion (combining uops) work. Apparently, those two techniques combined make the CPU effectively 40% wider in some situations, which is a very impressive gain in IPC, even if the average is lower.
C2D fetches at least 24bytes. It fetches and predecodes 6 instruction per cycle and average x86 instruction is 4bytes long.Quote:
Originally Posted by oldblue
http://castor.arstechnica.com/images/core2-uarch.gif
http://arstechnica.com/news.ars/post/20060626-7135.htmlQuote:
If you've seen the above diagram before, then you'll notice that there's a new number in there. From what I know, the Tokyo presentation is the first time that Intel has disclosed this much information about Core 2's fetch and predecode phases:
18-deep instruction queue
6 instructions can be written per cycle (by PreDecode)
5 instructions can be read per cycle
Implements a single "Macro-fusion" per cycle
Delivers complete instructions to the Decode stage
His comment hit the mark! AMD has not given a suitable answer to Conroe, so as it stands now they're just pumping out smoke. Anybody who doesn't realize this is just a fanboy in denial.Quote:
Originally Posted by nn_step
I'm sorry but stop right there, there was no stoping the Intel crowd doing that to AMD S939 when C2D Came out:rolleyes:Quote:
Originally Posted by Fr3ak
LOL! K8L outperforming current K8s by ~65% would be quite a feat.
I'll believe it when I see it and not before.
Where are my benchmarks?
as far as i'm concerned, the more hype there is without benchmarks, the more likely that that hype is wrong...
Since when do estimates by manufacturesr mean anything?
if you asked intel a while ago, they would tell you that 955 EE PWNS FX-60.
and ATI tried to tell us that the 7950GX2 was beaten by 20% by their x1900XTX.
on that note, I would be completely unsurprised if the 40% gain came from comparing a 2 clovertown platform to a 4 K8L platform, or comparing 2 clovertown V. 2 K8L both running at 2.4Ghz (with 2.4Ghz being the limit for scaling of K8L) theres no way to know without 3rd party benching. and NO, TASKMANAGER ISN'T A BENCHMARK!!!!!!!!!!:mad:
[/rant]
No, really, it is 16 bytes. X-Bit labs didn't make that up. Neither did Intel:Quote:
Originally Posted by gOJDO
It can predecode up to six instructions per cycle, but as you pointed out this would be rare because on average six instructions would be about 24 bytes, and the instruction fetch is only 16.Quote:
An instruction fetch is a 16-byte aligned lookup through the ITLB into the instruction cache and instruction prefetch buffers. A hit in the instruction cache causes 16 bytes to be delivered to the instruction predecoder.
But Core 2 also has 18 instruction buffer and the average size of an instruction is less than 4 bytes.
:confused: :confused:Quote:
Originally Posted by gOJDO
You have a cristal ball? You talk with such way that looks like you have all CPU´s in your ands and already tested then :rolleyes:
Slow down.... anyone know the truth. Only time will tell, so don´t be so radicall with those coments, or you can have a desilusion in your calculations :)
@oldblue
Yeap, you are right. It fetches 16bytes. I am glad that I learn from this forum. :)
Half of what Altair will be able to do.It will be one of the major advantages of the New Core,alongside handful of others.Quote:
Originally Posted by gOJDO
Anyone making any assumption about whether or not AMD is blowing smoke without seeing some actual results is a fanboy in denial.Quote:
Originally Posted by safan80
i don't why people are getting mad here. 40% more performance can ONLY be a good thing for everyone. because that would be one hell of a fast proc. and for WCG:slobber: :slobber: :slobber: ill take 10:D
so where's the es benchmarks???
am2 benchmarks are out 3 months ahead of release
c2d benchmarks are out 5-6 months before release
so where's the k8l benchmarks? nda is a bad excuse. show the money shots!!
Performance for CPU based application (Encoding, Archiving, etc) or graphical completed by GPU (Benchmarks, games, etc)? - you have to have a priority, most people think the same but some of us have different perspectives :).
sync up of r600 and barcelona, maybe?
HTX would definitely give an instant gain. Since the CPU could off load work to the GPUQuote:
Originally Posted by flclisgreat
completely not what i WAS thinking about, buts what i am thinking about now. i was the on the(dumber, now) track of a release syncQuote:
Originally Posted by nn_step
Can someone tell me where these numbers originated? Cuz I listened to the report and i'm almost positive that i never heard any mention of performance numbers, or Randy Allen for that matter. Did one of these sites interview him?
actually if they are crazy enough they could always make Quasi Delay Insensitive coprocessors. Since they can be made under 400,000 transistors and will wipe the floor with any other energy efficient design out there. Since they are "electrically perfect" and don't even need a heatsinkQuote:
Originally Posted by flclisgreat
true, but, C2D is being compared to a 3 year old AMD tech, quite funny that so many where shocked by the fact that C2D was faster then Athlon64. My point being months seem like an acceptable time span for comparison would'nt you agree?Quote:
Originally Posted by Fr3ak
Offcourse AMD's Stars CPU's will be faster then Intel's Core CPU's it is only natural progression of technology. Now 40% does seem like much but lets say thats the best case scenario against C2D and that actual average is 20% that means that Stars will be faster then Athlon64 chips by 40% (Because C2D's are 20% faster then Athlon64). Today you can actually find a benchmark where Opteron actually beats Xeon by a little bit, meaning if Xeon matches the Opteron performance in such test then the Barcelona based Opteron will actually beat Clovertown based Xeon CPU by 40%.
AMD's new core may be faster than Intel's C2D, but I'd really like to know how it's going to overclock.
If this new chip is so great, don't you think AMD would have used it to garner itself some positive publicity? It may be competitive but probably not as great as people tout it to be.
What about the girls? Can we call it 'fangirlism' for the girls?Quote:
Originally Posted by alucasa