The integer pipeline. That includes the loads & stores. With fp resources being widened, fp performance is taking a large jump-- what's left is the integer pipeline.Quote:
Originally Posted by Solus Corvus
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The integer pipeline. That includes the loads & stores. With fp resources being widened, fp performance is taking a large jump-- what's left is the integer pipeline.Quote:
Originally Posted by Solus Corvus
QFTQuote:
Originally Posted by flippin_waffles
2011 ;)Quote:
Originally Posted by Sn0wm@n
he still has plenty of time to sell his stock; he only thinks that trolling the crap out of a forum is going to give him another 1-2 months of rising stock prices (but it's extremely unlikely that some nerds like us posting on this forum are going to affext stock prices :ROTF:)
This is interesting bit from Question's Set no 2 @ AMD blog:
Quote:
“Is there any”programmable-tangible” improvement in synchronization between cores in the same module? In other words, will I get tangible performance improvement if I can partition my multi-threaded algorithm to pairs of closely interacting threads, and schedule each pair to a module?” – Edward Yang
That is a very interesting question.
For the majority of software, the OS will work in concert with the processor to manage the thread to core relationships. We are collaborating with Microsoft and the open source software community to ensure that future versions of Windows and Linux operating systems will understand how to enumerate and effectively schedule the Bulldozer core pairs. The OS will understand if your machine is setup for maximum performance or for maximum performance/watt which takes advantage of Core Performance Boost.
However, let’s say you want to explore if you can get a performance advantage if your threads were scheduled on different modules. The benefit you can gain really depends on how much sharing the two threads are going to do.
Since the two integer cores are completely separate and have their own execution clusters (pipelines) you get no sharing of data in the L1 – and there is no specific optimizations needed at the software level. However, at the L2 cache level there could be some benefits. A shared L2 cache means that both cores have access to read the same cache lines – but obviously only one can write any cache line at any time. This means that if you have a workload with a main focus of querying data and your two threads are sharing a data set that fits in our L2, then having them execute in the same module could have some advantages. The main advantage we expect to see is an increase in the power efficiency of the cores that are idle. The more idle other cores are, the better chance the busy cores will have to boost.
However, there is another consideration to this which is how available other cores are. You need to weigh the benefits of data sharing with the benefit of starting the thread on the next available core. Stacking up threads to execute in proximity means that a thread might be waiting in line while an open core is available for immediate execution. If your multi-threaded application isn’t optimized to target the L2 (or possibly the L3 cache), or you have distinctly separate applications to run, and you don’t need to conserve power, then you’ll likely get better performance by having them scheduled on separate modules. So it is important to weigh both options to determine the best execution.
Not when a marketing guy says it about "Bulldozer". Think of those 33% more cores, all processing instructions. ;)Quote:
Originally Posted by Solus Corvus
load/store performance is increased from K10...Quote:
Originally Posted by terrace215
just take your time and really think about it if you don't know it already
just stop trolling this forum if the only point in your posts is creating chaos
just stop hiding your real employer if you get paid by intel for spreading completely wrong information on this forum
Terrace, seriously, just give it a rest. If people don't want to listen to your view (whether it be wrong or right), saying it incessantly over and over isn't going to do much. You should know this, since people have been saying the same thing over and over to you, and you don't listen either, so, goes both ways ;)
Integer performance isn't all there is to a CPU's overall performance. There is a lot more to it than that. Come on...
Why not wait until the thing is closer to release and we have some harder numbers instead of this "he said she said they said" game that gives random tidbits for people to grab onto and wave around frantically insisting they have all the answers?
So you are saying that he invented a new definition for the term IPC because he's from AMD and can't possibly be using it the way everyone else does?Quote:
Originally Posted by terrace215
I think you've overstayed your welcome in the News section.Quote:
Originally Posted by terrace215
I'm removing your access to News and the AMD section for the benefit of all.
It's done. now lets move on..;)
That was a bit of a corporal punishment :p: ammm its ok to express ones view, if the other person does not like it he should ignore the other guy.Quote:
Originally Posted by Movieman
News section is one of the most happening section in XS :D but i am not one in charge or one who can judge. But i do think that now that he is gone the thread will turn boring with less people digging up technical jargon and what not....
The guy above somehow forgets that 2 integer pipelines are now "dislodged" from the integer core and placed inside the FP cluster.Those are integer SIMD units.So if you want to properly count, count all the integer resources .2 ALUs,2Agens(we really have no idea if these can do more than Adress Generation) + 2 or 1 integer simd pipeline.Quote:
Originally Posted by random now banned due
A good function to calc terrasse IQ :
short int terrasse(void);
terrasse{
return 0;
}
Ok this is a troll sry :).
About definitions we all should know :
Performance on one thread = IPC x Frequency
CPU Performance in heavy multithread load= IPC x Frequency x multithread speed up.
I guess i'm right ;)
Edited: Lets keep this friendly huh? My typing fingers are getting tired.
Yes it was but had you seen my PM box you'd understand.Quote:
Originally Posted by ajaidev
There comes a point where one needs tounderstand that they've made their point and move on.
I for one think that Movieman was more than patient with that due.Actually that is an understatement :)
I'm really sick of people posting in a thread only to comment about how someone else is a troll. So what if they are? Ad hominems still don't make for valid arguments or civilized discussion. These threads would be so much cleaner if people only remembered "attack the argument, not the person".
just put him on your ignore list, that's what I didQuote:
Originally Posted by Sparky
Hooray!!! Thats the best thing I've read all day.:yepp: It was funny in the beginning but he started to get a little annoying after a while. :shrug:Quote:
Originally Posted by Movieman
Hopefully the discussion will stay on what is known about BD and not what people dream up in thier minds.
I think once more info is released this thread will stay plenty activeQuote:
But i do think that now that he is gone the thread will turn boring with less people digging up technical jargon and what not....
Just wondering, what with all the chatter about bulldozer being 2+2 (alu+agu), aren't all intel cpus from core 2 and on 3+1? Correct me if I'm wrong, but if that's the case and the grand majority of consumer applications don't use more than 2 alus at a time, then I don't really what the issue is.
Now what I can see being an issue is Sandy Bridge performing considerably better than expected (I recall many rumors saying it was just an efficiency platform, and minimal if no ipc improvements would be seen), however that really isn't a discussion for this thread anyways.
Wise words, but people resort to personal attacks if they have no or limited understading whats going on... :p:Quote:
Originally Posted by Solus Corvus
While its true that they are only 3+1 conroe introduced a 4(+1) for the decoding stage, just as BD did now. So the utilisation of the alus is/was higher.Quote:
Originally Posted by AliG
thanks for the update from round 2, i was waiting for this, he posts a thread in the AMD section, but im too busy here to check it out every 5 minutes.Quote:
Originally Posted by ajaidev
the round of questions do provide some more fun info, and the comments are where the real goodies show up across the next few days
It may not refute the argument, but if someone is genuinely a "troll" they don't really deserve to be able to participate in a civil discussion. Thread crapping when a person can't prove an argument or disprove one they dislike does nothing but detract from the quality of the overall debate.
Nothing personal against "terrace215", or anyone else... Opinions are just that, opinions! Everybody has one, just like they have an a$$#0L3... Facts, we will only find out when someone perhaps will leak some numbers... I did read in forums here only that somewhere in a cave in my own damned country, there's a system running this piece of hardware in question... A whole 16-pack (for as many cores) :P will be given to you dear fella... find out more please! You know who you are...Quote:
Originally Posted by Movieman
Movieman, if you come to New Delhi, India, do sound me off, i'll buy you a beer. :)
I just wish that it would be here soon... :P More pleasurable than owning the chip itself would be knowing what black magic went into making it :D
EDIT:
1) Ok, i had to apologize for my language...
2) Seriously getting harder to decide which would be more fun, owning one... or knowing about it more... :P Both, would be better :D
Quite interesting, by that definition he wasn't a trol lat all. He provided a logical argument/question with some facts (even when they where old), yet people had no real facts to counter his spesific question (ST IPC). The only facts that where available where increased ST performance and increased IPC (not specifed if its ST or not).Quote:
Originally Posted by Particle
Anyway personally I prefer hard numbers, so all this theoretical mindgames arn't my cup of tea.
Prefetching and branch prediction plays a major role for high utilization of ALU / FPUs.Quote:
Originally Posted by AliG
As stated before, most programs have IPC of < 1.0.
right that's what I thought, because otherwise we would be seeing zero increase from core 2 to sandy bridge as primarily only the logic and prefetchers were changedQuote:
Originally Posted by qcmadness