!!!The Ultimate K8L Thread 2007 & Beyond!!!

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03-05-2007, 07:44 PM
i found nemo

30 - 40% faster than current k8 is a lil faster than cd2
03-06-2007, 12:07 AM
Turtle 1

Got a link to these so called benchmarks that we can all view . I want to see real benchmarks. Less than a month ago same people saying K10 here in april may . Now its been confirmed the end of summer maybe. The same people questioned these forcast also . So far the none believers are smoking the believers big time. I am willing to bet on the 20to 30% performance in benchmarks . This has to apply to allmost all benchmarks.

You name the stakes . Remember Intel has said bearlake brings a 10 to 15 % increase in C2D performance . You name the stakes . I will take the bet. Bearlake is going to be here way before K10. Fact is its looking like Penryn will beat K10 to the post
03-06-2007, 12:40 AM
Dresdenboy

Some people here forgot, that having Barcelona ES in their hands or Barcelona dies on a wafer doesn't automatically allow AMD to sell the CPU to all 5 tier one OEMs, which are waiting for it to arrive. Being able to sell (!=giving ES away) means to have a good yield and enough wafer starts to fulfill expected demand.

Since it looks like AMD already has problems to fulfill demand (esp. of the channel, which comes after the OEMs) while having a CPU performing worse than Intel's offering - how would they fare selling a CPU which might be at least a bit better than Clovertown without having exaggerated price points?

BTW, something to complete the picture of the current situation for servers:
http://tweakers.net/reviews/674/1
03-06-2007, 12:51 AM
Dresdenboy

Quote:

Originally Posted by LOE

I doubt a chipset can bring 15% more performance, something like that has never happened before, and probably won't happen now. I just don't see anything that could bring that kind of performance. Higher FSB could benefit quad core chips, higher mem bandwidth could also do the same thing, but by such margin.

http://www.hkepc.com/bbs/itnews.php?...me=0&endtime=0

Increasing memory bandwidth for QC has much more significant effects than it has for DC or even SC. Just think of FSB contention in tasks, which can't make efficient use of the caches thanks to huge datasets. I think, with optimized handling of mem accesses (maybe even with prefetching by the chipset itself), DDR3 and the higher FSB bandwidth you could see double digit improvements as they claim. Except maybe for Cinema4D and other apps/benches running nicely in the caches ;)
03-06-2007, 02:16 AM
Shintai

Quote:

Originally Posted by LOE

Well there is some "info" floating arround the forum, that K10 at 2.4 Ghz outperforms conroe @3.6 Ghz by 15-18% in a certain heavy calculation app

And AS FAR as I could understand AMD info, K10 will be up to 80% faster than K8
And that 40% lead in FP is over quad core xeon at 2.66 Ghz

I'd say K10 will be about 20-30% better than c2 on average, with some performance variations depending on the type of benches used

Whan we know so far is that K10 will have double the FP power of K8, also will bring atleast 20% more performance due to the new prefetchers, I dunno about the DRAM prefetcher but it should show some advantage in games IMO. There is also the L3 cache that will affect performance

Thus we do not have any hard numbers I'd day K10 has a very good chance to crush core2, at least in the apps I am interested in, rending, audio and video editing and processing.. After all that are the apps that make use of fast processors, I don't think it is that big to open word for 1 instead of 2 sec. Thats double difference but 1 sec is nothing. Now comparing to rending a scene 3 hours vs 6 hours per scene makes a big difference, having in mind you have to do like 20 scenes :)

Please...down to earth. Or you gonna be heavily dissapointed.

K10 wont have double the FP power. It will potentially have double the SSE power.
K8 already beat Intel with 20% or so in this "FP" benchmark of theirs. Also called specFP_rate. Please visit www.spec.org Its nothing more than a semi memory benchmark and PR spin.
And did you notice the QUADCORE K10 was 80% over a DUALCORE K8? Amazing aint it....

The more real information is that K10 is about 10% faster than Core 2 clock for clock with all enchancements.
03-06-2007, 03:52 AM
informal

Quote:

Originally Posted by Shintai

K10 wont have double the FP power.

The most obvious improvement is the second fpu pipe...Alongside the other mentioned in the huge list of improvements.
03-06-2007, 06:59 AM
arisythila

Want to have 4 threads going? LOL
03-06-2007, 07:13 AM
arisythila

Grarge.. We have to talk about K8L in this thread, and not wanting to go through 29 pages. lets just go back a few pages.

I remember AMD saying that the FPU power would be 3.2 times faster than K8's I'm not exactly sure how it got like that tho. They factored in that because it has 2 extra cores, and all the enhancements that the K10 has. I do remember them saying something about 3 complex FPU pipes I have to find that.

~Mike

EDIT: AMD said they do 4 instructions per cycle, over what K8 does 2 instructions per cycle.
03-06-2007, 07:32 AM
Shintai

Quote:

Originally Posted by arisythila

EDIT: AMD said they do 4 instructions per cycle, over what K8 does 2 instructions per cycle.

Uhm...thats nothing to do with any extra FPU. And its not any type of instruction either. They increased the SSE output from 2 double precision instructions to potentially 4. This affects SSE only and its only due to its being widen from 64bit to 128bit. Its like saying C2D got 6x more FPUs than CD :slap:

So...same amount of FPU units.
03-06-2007, 07:34 AM
arisythila

Just saying what AMD said. LOL

~Mike
03-06-2007, 07:45 AM
Dresdenboy

Quote:

Originally Posted by arisythila

EDIT: AMD said they do 4 instructions per cycle, over what K8 does 2 instructions per cycle.

They surely said something like "4 DP operations per cycle", which you can achieve by using 2 SSE2 instructions per cycle. BTW these FLOP numbers usually only count arithmetical ops like addition/multiplication etc.
03-06-2007, 08:18 AM
Fred_Pohl

Quote:

Originally Posted by shintai

The more real information is that K10 is about 10% faster than Core 2 clock for clock with all enchancements.

Given the actual core changes, that are well-documented at this time, that's a lot more believable than the 40% fanboy fantasies being opined by some.

Quote:

Originally Posted by Dresdenboy

They surely said something like "4 DP operations per cycle", which you can achieve by using 2 SSE2 instructions per cycle. BTW these FLOP numbers usually only count arithmetical ops like addition/multiplication etc.

Doesn't C2 already do 2 SSE2 instructions per cycle?
03-06-2007, 08:40 AM
savantu

Quote:

Originally Posted by Dresdenboy

http://www.hkepc.com/bbs/itnews.php?...me=0&endtime=0

Increasing memory bandwidth for QC has much more significant effects than it has for DC or even SC. Just think of FSB contention in tasks, which can't make efficient use of the caches thanks to huge datasets. I think, with optimized handling of mem accesses (maybe even with prefetching by the chipset itself), DDR3 and the higher FSB bandwidth you could see double digit improvements as they claim. Except maybe for Cinema4D and other apps/benches running nicely in the caches ;)

If you're the same guy who posts at Aces , you definetly sound more knowledgeable there.:slap:
03-06-2007, 09:06 AM
informal

Brent i am seriously starting to doubt your knowledge of CPU architecture!
The 2nd FPU unit is CLEARLY visible on die shots of Barcelona!
http://www.chip-architect.com/news/K8L_floorplan.jpg

Next time get your facts str8 before you accuse someone of lack of knowledge.
03-06-2007, 09:15 AM
informal

Quote:

Originally Posted by brentpresley

MY POINT WAS K8 ALREADY HAD 2 FPU UNITS!!!!!

MEANING THAT NO ADDITIONAL FPU UNITS WERE ADDED. :slap:

:owned:

If you are so in "owning" mood ,please show me on the next picture the second FPU pipe at the revF(circle it in some photo app):

http://pc.watch.impress.co.jp/docs/2...2/kaigai_4.jpg

http://pc.watch.impress.co.jp/docs/2...2/kaigai_4.jpg

And please show it at this Brisbane die shot:
http://pc.watch.impress.co.jp/docs/2...gai267_03l.gif

Here's what Dirk M. said in the interview:

Quote:

With the Hound core, 1 floating point arithmetic pipe is added to the side of the existing floating point arithmetic pipe already.
03-06-2007, 09:34 AM
informal

So what did you show me exactly?And where is the circled image i requested from you?
AMD just doubled all the resources you showed in that diagram...
I am still awaiting for you to point out the RevF second FPU unit!Oh wait,it is not there...Doh
So much for getting ownd:rolleyes:

edit:Just for you,i quote once again the good 'ol Dirk M. :

Quote:

With the Hound core, 1 floating point arithmetic pipe is added to the side of the existing floating point arithmetic pipe already.
03-06-2007, 09:41 AM
informal

Brent i am getting tired of your personal attacks.It's clear you don't understand what you are trying to say.Look at chip arch. floorplan and everything will be clear to you.
They reorganized the scheduler and doubled the resources from there on.Decoders stayed as they were.
And you want to call Dirk Meyer from AMD the clueless man?Ok suit yourself.
I'm not gonna waste my time any more with you.
03-06-2007, 09:47 AM
informal

SO Hans De Vries version i linked after is not good enough for you??
Cmon ,that si a lame excuse to get out without admitting you were wrong...
Yeah old die plots ...Whatever

Here:http://www.theinquirer.net/default.aspx?article=29890 Charlie talks about K10 and mobile version of it(which lacks the second FPU unit since it's not needed in the mobile sector)

http://www.pureoverclock.com/images/review/k8l_fpu.gif
03-06-2007, 09:58 AM
[XC] Teroedni

Quote:

Originally Posted by brentpresley

And here is a MUCH better die shot from and Anandtech article less than a week old.

http://www.anandtech.com/cpuchipsets...spx?i=2939&p=2

Now, where is that extra FPU per core?

You mean you cant see it?
I can clearly see that the Fpu is doubled:D
03-06-2007, 10:00 AM
informal

Brent,can you see this floorplan?
http://www.chip-architect.com/news/K8L_floorplan.jpg

Now compare it to your AT link.
Tip:The difference is in rotation of the core.You will (i hope at least) notice the parts which Mr. De Vreis highlighted for us so conviniently .
03-06-2007, 10:12 AM
informal

Oh i give up.I can't waste any more time with you on this.Believe what you will(who says AMD needed to double the number of decoders??? You want to say you know more than Hans De Vreis when CPUs come to question?)
Feel free to email him and ask him the same question.I really want to know what will he tell you:rolleyes:
03-06-2007, 10:19 AM
SEA

Guys, stop slashing the water.

We already discussed everything.

AMD did NOT add more FP processing units (this is not about store or loads), but
They widened them the way to crunch 1 SSE128 in EACH FP Unit at once. That is 2x SSE128 at once.
Also you miss the thing that those units can perform 2xSSE64 EACH AT ONCE.
That means the doubled throughput of SSE64.

So it is true about doubling SSE performance, and it is true that they did not add additional SSE FP units

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