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Thats true. But we do know how it performs in a very very cold room. I thought the test that got 3.1 ghz . The temps were reading wrong. But Anand test should no such problem . So I believe they were the correctly reported temps now. The room was very cold . Window open . heat register off.;)Quote:
Originally Posted by Lightman
Not really nn as the good conroe chips hit 4ghz . No reason not to believe with a good shrink and High K gates 4+ ghz should be easy. But well have to wait and see won't we . For now its just hoping.Quote:
Originally Posted by nn_step
thats cute, but conroe already ocs to 3.5-3.7, i see you have read the anandtech rd600 review, but i guess you conveniently missed the part about the 3.9ghz 6600 on air... granted thats above average, but youre a little confused if you think 45nm wont increase the clock speed beyond 3.7, when its already possible with current chips...Quote:
Originally Posted by nn_step
Similar not --- Intel's is quite superior, Idsat is 10-15% higher, hence Td (gate delay) is lower, thus faster clocking chips.Quote:
Originally Posted by nn_step
http://www.realworldtech.com/page.cf...3005001504&p=7
Also account for the fact that the buried oxide is not only a poor electrical conductor (good for short channel effects, SCE) but is also a poor thermal conductor, then add in that SOI transistors have a self-heating propensity and it all adds up to AMD processors being poor overclockers relative to Intel CPUs in general.
Also, K8 has 12 stage Integer/ALU, and 17 stage FPU (as I recall, someone may want to correct me) ... the average mix of instrutions fetched/decoded and dispatched will depend upon the application at hand, but on average you can basically consider the stage length to be slightly more than 12. It is not unreasonable though abit of an approximation to claim that C2D and K8 are approximately the same, C2D being slightly longer.
A quad core at 3.7 ghz on air? :slobber:Quote:
Originally Posted by nn_step
yea, 3.7 on air but still is there any good performance increase......i don't see any significant, like Conroe but maybe this is like a test and just to see how it works and if its successful then they will take it and run and improve it some more for K8L
umm NO because 12 != 14 (does not) and 17 != 22Quote:
Originally Posted by JumpingJack
Intel has 2 More Integer stages and 5 More FP stages
and the So called superior Process that you are talking about...
umm you liked to the process that made the world's HOTTEST Processor (Prescott) which I would not call a Superior process, rather a mistake that intel didn't fix till 65nm.
And PLEASE notice the Term "AVERAGE" in the above statement. Conroe is NOT Jesus reborn, rather a Good Processor design on an EXPENSIVE but very effective Process.
AMD lacking the funds to go to such extremes, follows a simple logical rational path.
I want Competition, not one being superior. Cus Who EVER wins, we lose :fact:
told, the changes shrink the Pentium 4's die size to 122 mm 2 , from 145 mm 2 for Northwood—this despite the fact Prescott's transistor count is 125 million, over twice Northwood's 55 million transistors
With 2MB cache on each core, the transistor count of Presler has gone up a bit. While Smithfield weighed in at a whopping 230M transistors, Presler is now up to 376M. The move to 65nm has actually made the chip smaller at 162 mm2, down from 206 mm2. With a smaller die size, Presler is actually cheaper for Intel to make than Smithfield, despite having twice the cache. Equally impressive is that Cedar Mill, the single core version, measures in at a meager 81 mm2.
AMD Athlon 64 X2: CPU: 154 m Intel Core 2 Duo: CPU: 291 m
So which process do you think is better?
there was nothing wrong with intel's 90nm process, it worked perfectly fine on dothan. i pefectly understand that competition is crucial, but amd doesnt seem to be doing much outside of the markets that bring in the most profit, and its showing in its dekstop peformance, no matter how much you try to sugarcoat it. do you thnk that we forgot the endless fud you used to spread, how you used to sound in the know and so knowledgeable amd how each and every one of your predictions turns out to be horse manure. you have done great work with the xtremesystems os, and im sure everybody appreciates it, but stop posting pro-amd fud already...Quote:
Originally Posted by nn_step
You're right, but it is not entirely true that hard clocking limit is in number of stages (like other post are suggesting). The real limiting factor is signal propagation on long lines (buses). If your new fabbing process can speed up movement of electrons then you can reach higher clocks (if other factors are not limiting you). What I'm saying is that CPU with 9 stages can clock higher than CPU with 14 stages if former one is on better process (or latter is on plain). That is a reason to introduce DSL, SSDSL, SiGe, etc. So claiming that new fabbing revision with addition of SiGe won't change anything is simply wrong. What we don't know is how much this will improve clocking, certainly not 40% because this much is from bulk process. I personally am expecting 15%-20% improvement over actual mix AMD is using.Quote:
Originally Posted by brentpresley
:toast: for everyone!
A good view on the diminishing returns issue might be the P4 90nm to 65nm. There is just too many changes that you cant just fix. And the P4 even had a major update in the prescott. Its been the same way all time in history. After a few process shrinks it just stop in terms of clock returns due to design limitations.
Not true The Prescot would clock much higher but heat became an issue along with memory bandwidth. The heat issue in the long run could have been dealt with. But for P4 to effectively scale up badly needed an ondie memory controller. P4 was a bandwidth hog. an ondie memory control would have scaled the number of transitors down alot as cache could have been smaller. Were intel really screwed up was going to prescott from northwood.Quote:
Originally Posted by Shintai
I would have loved to seen northwood @ 45nm.with ondie memory controller. Who knows I may get my wish . Will see how many pipelines are in Nehalem. IF 18 I well call it a Northy.
Ahhh --- you have been pre-programmed by the machine I see....Quote:
Originally Posted by nn_step
However, to understand what I mean by superior process would take more time that I have. I linked the data, it is clear.
Intel's 90 nm had no problems, it was in design. Period. A crappy, inefficient architecture will be crappy no matter what process you put on it. To understand this concept, take a Pentium-M for example, shorter pipeline, same 90 nm process but when clocked to desktop speeds, actually goes neck and neck, and in may cases out performs an FX-60 (clocked to 2.8 GHz), using much less power:
http://www.matbe.com/articles/lire/2...nce/page21.php
http://www.matbe.com/articles/lire/2...nce/page19.php
clock for clock a 90 nm Intel cpu beating an fx-60 at lower power consumption who wudda thought.
It is unfortunate more sites did not push the Pentium-M to see what it would do, and it is perplexing why Intel stuck with Netburst so long when it was clearly inferior.
Now, on to your argument that 'it took 65 nm to fix', if you read the reviews for cedarmill/presler -- those were also hot running chips. It is inappropriate to draw the conclusion you are drawing comparing two class of CPUs and extrapolating back that it was a process problem when the end result of power and IPC and clock is a convoluted function of both process and archtecture.
The fact, it is a fact, remains that Intel produces cooler running transistors that switch faster, node for node when compared to AMD.
This is not a deficit that cannot be overcome, obviously, AMD did one heck of a fantastic job on K8, and will do so on K8L I expect, but they overcame their process deficiency with a good architectural design --- which relied more on Intel making a mistake more than domineering IPC in order to get a nice performance lead. Credit to AMD, but Intel has now changed their design philosophy and it will be much harder for AMD from here.
Same could have been said about Northwood. However You forget that Intel updated its 90nm ALOT. Prescott was on a process that did have leakage current and alot of it. Later Processes did reduce that greatly and those later processes were used by your Pentium-M. To say Intel just developed 90nm and then moved on to 65nm is ridiculous. Should Intel have Gone the Via route, their Design would have scaled to 10Ghz. However all that extra useless logic did nothing, Netburst in Theory was a Wonderful design and will probably be used again in the future. However I doubt we will see an OoO processor hit 10Ghz this Decade
Thats true nn When Intel first used Ssilicon on 90 it bad leakage problems . It wasn't until they got the right mix of Ge that the process improved. Couple that with 2x the transitor count. Things were bleak. Had Intel stayed with the Northwood . The heat wouldn't have been as big an issue @ 55 million transitors.
When was Dothan released compared to Prescott? Dothan improved 1 single speedgrade in its entire life. I guess that covers your 90nm improvement?Quote:
Originally Posted by nn_step
Dothan, may 10th 2004.
Prescott, february 1st 2004.
Unlike others, Intel got the ability to release top speedgrades at introduction.
Dothan was designed to operate on laptops within a power envelope. Since it had no competition there was no need to push that envelope. But I thought there was more than one speed ramp.Quote:
Originally Posted by Shintai
I think there was a bit more than one speed bump LOL. I didn't take time to get list of them all but this says most of it. Shintai I was banned for a week for less offense than your post. See that little triangle on your left . I have used it once in my life. Unlike many that use it like a chess speed timer.
IntelŪ PentiumŪ M Processor with 2MB on-die cache
Speeds at 1.67Ghz-2.50Ghz (Dothan), 400 & 533Mhz FSB
It's the end of December. I see no K8L. :(
umm it isn't expected until 2H 2007Quote:
Originally Posted by LordofDoom
the es was ssupposed to be around starting in the end of 06. obviously, k8l isnt ready for that yet since their demo was task manager.Quote:
Originally Posted by nn_step
:) :) Look, I am not here to start a fanboy flame war..... the opinions/facts vary on this all over the place.... you make a good observation here though, Intel refines it's process just as AMD refines theirs over the lifetime of the technology.... many do not believe this, always stating Intel does one big rev and AMD keeps tweaking.... this of course is not true, they always tweak up their process. However, Prescott sucked not because of leakage, it just sucked period :).... the leakage argument is a subjective analysis imposed by HW review sites who extrapolated this conclusion based on emprical observations on one architectural revision of the process.Quote:
Originally Posted by nn_step
Take for example the 65 nm Presler and Cedarmill, they were more or less dumb shrinks of Prescott --- but had exactly the same power problems at top bin --- is anyone saying the 65 nm process is leaky??? Nope, because there is Yonah and Conroe that manage power very effectively.
My point is --- you cannot take the emperical observation of a power meter stuck to a wall socket and the stability of a system at top clocks and directly extrapolate who has a better process easily --- in fact, it is a moot point. The process is 1/2 the equation, the other 1/2 is design/architecture. A good designer can take a substandard process and make a powerful CPU that simply SIPs power. In fact, AMD's sleep states and C&Q are quite advanced, and are certainly showing up in their idle power metrics.... does this make the 90 nm process superior, in some people's eyes yes.... but this is an architectural state not a transistor leakage state... there is a huge difference.
Again, I linked the data above which showed the industry accepted tansistor parametrics for transistor performance (Idsat, high/low Vt, etc) -- how those transistors are utilized to make a CPU is up to the designer and if it is a good design the processor will do well.... as I showed with a Pentium-M on a 90 nm process clocked at 2.8 GHz.
The data is out there to get to the fundamental of the process without the architectural portion of the equation, you just have to look for it....
You are incorrect though that Dothan/Banias/Prescott etc were processed at different times on different processes --- both mobile and desktop processed right along all the way until 65 nm came on line. Dothan was introduced with Prescott at the same time (actually about 2-3 months apart), fabbed at the same time -- Prescott released on or around Feb 2004, Dothan on or around May 2004. I doubt, if Intel made such great improvements in 90 nm leakage for Dothan that it would not have been shown to improve the same power metrics on Precott in 2005 :) ...
http://badhardware.blogspot.com/2006...70453330892136
Thats what I thought. HT3 will be independently on core speed!
am2 southbridges nowadays have 5x HT, future am2+ will have 13x
Not much time left for AMD to send out those December K8L ES chips...
I guess I'll just have to file this rumor together with the 50% higher clocking Brisbanes with 4MB of ZRAM L3 cache and 25% performance boosting RHTT. Speaking of which, I emailed Charlie D. of The Inq in response to his latest rant about hardware reviewers expecting too much from Brisbane to remind him of his rag's 2006 predictions of Brisbanes being officially announced in March, shipping in June, containing 4MB of cache, clocking 50% higher and all K8s getting a 25% performance boost from RHTT but he didn't seem to appreciate it. ;)