250mm3 quad-core cpu's, I guess they will NEED voltage adjustment for each seperate core :rolleyes:
EDIT: Ofcourse because of scaling problems that would occur with such a large die.
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250mm3 quad-core cpu's, I guess they will NEED voltage adjustment for each seperate core :rolleyes:
EDIT: Ofcourse because of scaling problems that would occur with such a large die.
That's for the servers... I wouldn't be surprised if half of those features weren't supported on the desktop versions.
Quote:
Originally Posted by Cooper
Good Catch!!!
That is one tiny little cache!
And one slow cache. I think it would still need a faster L2 cache besides it. Maybe they can make the cpu as fast but smaller using this tech by making the L2 cache very small and the L3 cache much larger in kb with this tech.Quote:
Originally Posted by Revv23
If the FPUs are 2x64, then I doubt the K8L will have the 1 cycle throughput that Merom and Conroe has.
But I may be wrong.
That may be true, but then K8L will have nearly double the FPUs as that of NGMA. It'll also have one more SSE unit than the NGMA.
Nice, AMD effectively killed most early AM2 sales. I know I will be sitting on my hands and wallets and see what K8L offers before I switch platforms.
Mmmmm DDR3 :D
How slow is it :stick: I imagine AMD would make it quite a bit faster than the DDR2/3 RAM or it's not even worth having it on thereQuote:
Originally Posted by alexio
As far as the latest data (that I have read anyway) on Z-Ram is concerned it is slower than conventional L2 Cache.Quote:
Originally Posted by Repoman
Only when the capacity is below 2Mb ;) the larger the Cache the faster it is compared to traditional CacheQuote:
Originally Posted by MaxxxRacer
I figured that, only makes sense that L3 cache will be slower than L2. L1>L2>L3, but you can only have so much the fastest levels.. imagine 4MB of ~23GB/s L1, no need for anything elseQuote:
Originally Posted by MaxxxRacer
It has 2x128 bit SSE units (ADD+MUL) and can handle up to 4 DP FLOPS/cycle. Conroe can do exactly the same thing.Quote:
Originally Posted by Shadowmage
http://news.com.com//i/ne/p/2006/amdslide4_532x402.jpg
Don't you love the Irony.. I was saying DDR3 and was getting ripped upon by it because of AMD slides yet now AMD slides seem to agree with me after all.. :p:
The smart people were already doing this :p:Quote:
Originally Posted by situman
You said AM2 would use DDR3 right? This is not quite AM2, this is K8L and will follow after AM2.Quote:
Originally Posted by nn_step
Keep on playing in your little dream world. You got ripped because you were pulling things out of your uninformed ass. Oh gee, you're such a genius for predicting that after DDR2, AMD would be going to....wait for it....almost there...DDR3!!!Quote:
Originally Posted by nn_step
You just don't know when to stop embarassing yourself. You're clueless.
M2, AM2 is something a little bit different ;)Quote:
Originally Posted by alexio
Some smart people sometimes needs a little more persuasionQuote:
Originally Posted by Bar81
Fair enough :DQuote:
Originally Posted by situman
IF they both do perform quit well, there are some questions.....Is AMD going to drop prices so as to be competitive?....coz if not, they will lose the game......;) .....Are the AMD's new CPUs NOT going to have a cold bug problem?.....coz if they DO have a cold bug problem and Conroe don't, they'll lose as overclockers.....;)Quote:
Originally Posted by NickS
I think the cold bug question is a long dead one. After discovering the reasons for the cold bug, it seems likely that they will not be fixed in later iterations of AMD CPU's unless there is a HUGE redesign of the entire arhcitecture.
BUT I could be wrong.. (kind of hope that I am)
If nV could patch up G70-256's coldbug (bugged for very similar reasons) for the G70-512 and G71, I'd bet AMD can do it. Whether or not they will is another story. I would really love to see non-CB'd AMD chips and have real competition at the top for a sustained time. The CB is damn annoying on a few levels (not that I've ever run into a problem with the coldbug (even with DICE, lol)).
Can we please get off of this argument? It seems every AMD thread leads to an nn_step bashing. Does it really matter if he's BSing people or not? It's not like he's giving up any useful information.Quote:
Originally Posted by Bar81
Floating point is conroes weakness, Int is conroes strong point. Doubling the FPU on K8L will allow it to MAUL conroe in floating point calculations, they won't even be on the same page.Quote:
Originally Posted by keiths
Also, if it's more efficient at those extensions, like it should be, that would allow it to do them in less cycles, which would increase the IPC, no?
Actually.... Am I wrong in thinking that 130nm A64's didn't have the cold bug? If I'm not mistaken(I could be as I don't do sub-zero) it wasn't until winchester that the cold bug showed it's ugly head... If that's the case, there's a 50/50(130nm didn't vs 90nm did) chance that A64's at 65nm won't have the bug, right?Quote:
Originally Posted by MaxxxRacer