Mushkin 2GB XP4000 Redline CE-5 – Test Results

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Originally Posted by JNav89GT

My kits a bit different. I'm getting about 280-281 max, but taking 2.9v to do it. My kit just doesn't want to fly with low volts like Donks and Bacchus. Oh well still happy :)

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280-281 is very good, I would be happy too. :)

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Originally Posted by _damien_

Curious. I've seen overclockers point out that connection before, but I am confident that the theory doesn't hold water. Not that I'm accusing anybody of making it up, I'm just wondering what could be the cause. Of course, just because a low ICL is not *supposed* to cause instability, doesn't rule out the possibility of BIOS-bugs, etc.

Great result, no doubt about that! Is the last screenshot @ 2.85 vDIMM?

A suggestion: Loosening the tREF would free up the command bus, and in a sense give higher priority to the actual CPU-requests. One of the 7.8us-settings should suffice to maintain data integrity. A low value will hurt memory efficiency and possibly reduce stability (but of course, if set too high the data could expire). When a row is refreshed, the capacitor charges of thousands of memory cells are sensed and amplified, then restored to the row again. The amplifying implies rather massive power-surges, which can cause unwanted electrical side effects like noise and voltage droops, so the memory shouldn't be refreshed more often than necessary. When I changed from 133MHz 3.9us to 133 7.8us I gained around 200 MB/s in the Sandra BW-test, even though I'm on single channel.

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Last SS is @ 2.7 + .03v in BIOS, about 2.82-2.83v w/ DMM.

I usually test tref by running bandwidth benches. I find in general 166 -1.95us and 100 - 1.95us give some of the better bandwidths for most RAM but I can test out 133 7.8us this evening for comparo. :)

Question.. If I understand your ICL post correctly, you saying that all mem should be able to run 0clks without instability? I found from tests in the past that higher voltage RAM like utt or bh-5 could run 0 clks fine but mem with overall looser timings like TCCD and UCCC had issues w/ 0. Interesting to hear how ICL actually works, all I knew is PI likes lower heh. ;)

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Originally Posted by Eldonko

Question.. If I understand your ICL post correctly, you saying that all mem should be able to run 0clks without instability?

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That's what I'm saying :) Delaying the precharging by a fixed number of cycles doesn't really change much, electrically. The precharges would occur just as frequently, the only difference between e.g. 0 and 64 is that the latter will allow a recently accessed row to remain active for up to 64 cycles (after having completed a transfer), before it is forcibly precharged. So if the CPU later requests data from the same row, there's no need to sense/amplify it again (tRCD). In that case the data will be output after the completion of tCL - the only delay involved.

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Originally Posted by Eldonko

Interesting to hear how ICL actually works, all I knew is PI likes lower heh. ;)

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If an application prefers low ICL that's an indication of many random memory accesses, as opposed to sequential, well organized reads. Typical examples of applications with random patterns are games, or "unpredictable" tasks as a whole. SuperPi probably has a pretty straightforward access pattern, so I guess the lack of modern optimizations could be the explanation to your finding.

First post updated, scaled to 287Mhz 3d and 32m stable w/ 2.8v (BIOS) 2.88v (DMM). :)

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Originally Posted by Eldonko

First post updated, scaled to 287Mhz 3d and 32m stable w/ 2.8v (BIOS) 2.88v (DMM). :)

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Awesome! :up: Can it survive looping of 3DMark2001 for any substantial amount of time? I can also bench mine in 3D @ same 287MHz but it's no good for some prologed gaming or looping - it will freeze very often.

Not sure yet, just finished testing to 287 a few mins ago, gunna bump .03v and see if I can get to 290. :p: Will loop 3dmark01 as soon as I can.

283 had no gaming issues at all, I let my brother hang at my house and play BF2 all day when I was at work. I dont have the time to play many games so my lil bro takes care of those tests for me heh heh.

Did some 2.5-3-2 testing tonite, cant touch your set w/ CAS2.5 bachus, best I can do 3d benches with is 260Mhz and it needs alotta volts. No way is cas 2.5 worth losing 25Mhz.

Updated 1st post. :)

ELdonko,

Some very nice mem there, i might have to see if I can get my 3500LLPro to perform at 287 like yours :)

SAD

Hey SuAsDu! Thanks and GL :)

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Originally Posted by Eldonko

Did some 2.5-3-2 testing tonite, cant touch your set w/ CAS2.5 bachus, best I can do 3d benches with is 260Mhz and it needs alotta volts. No way is cas 2.5 worth losing 25Mhz.

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Indeed not. The real difference is when tightening from 2.5 to 2.0, but the performance difference between 2.5 and 3.0 is tiny.

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Originally Posted by Eldonko

Did some 2.5-3-2 testing tonite, cant touch your set w/ CAS2.5 bachus, best I can do 3d benches with is 260Mhz and it needs alotta volts. No way is cas 2.5 worth losing 25Mhz. Updated 1st post. :)

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My set could do 260Mhz 5-2-3-2.5-1T at same 2.58v (DMM) it maxed out at CAS3.0 in 3D but 270Mhz required hell of a bump in voltage.
If it reaches high at CAS3.0, then CAS2.5 is "just for show". Gains, even at same speed are very small, even from bencher's point of view.

This price drop is worth a thread bump, get it while you can. Link