AMD new E6 revision replaces E3 one's

Printable View

Show 100 post(s) from this thread on one page

06-09-2005, 07:26 AM
Crosis

I would like to how they will be o/cin' according to Venice...
06-09-2005, 07:43 AM
eva2000

Quote:

Originally Posted by dimasdw

@s7e9h3n
acording to your screenshot BV is Toledo :D
and CD is denmark (X2 with 1 Mb L2 Cache)
http://www.watch.impress.co.jp/akiba...mage/nx2d2.jpg

:slobber: :slobber: :slobber:

That yours ? :)
06-09-2005, 08:07 AM
s7e9h3n

Quote:

Originally Posted by dimasdw

@s7e9h3n
acording to your screenshot BV is Toledo :D
and CD is denmark (X2 with 1 Mb L2 Cache)
http://www.watch.impress.co.jp/akiba...mage/nx2d2.jpg

@STEvil

so BP is venice with rev E3 and BW is venice with rev E6 right ?

Gee thanks :rolleyes: , I know it may be hard to believe, but you can't always trust cpu-z's ID's. This is the exact same cpu as above (I sent it to OPB):
http://www.ocxtreme.org/onepagebook/.../pcmk0494k.jpg
06-09-2005, 08:17 AM
situman

so E6 revision chips are still dual channel? Its just a failed dual core?
06-09-2005, 09:03 AM
panumas05

E6 in Dual core.

http://www.xbitlabs.com/articles/cpu...on64-x2_3.html

But new BW is disable Dual core and disable cache ?
06-09-2005, 10:01 AM
metro.cl

weird anyone can tell more???
06-09-2005, 10:17 AM
setyotomo

@s7e9v3n : 9476 PC Marks :banana:
06-09-2005, 10:57 AM
[XC] leviathan18

i dont think disable core disable cache is more likely to be faulty core or cache
06-09-2005, 11:03 AM
terrace215

Quote:

Originally Posted by dimasdw

@s7e9h3n
acording to your screenshot BV is Toledo :D
and CD is denmark (X2 with 1 Mb L2 Cache)
http://www.watch.impress.co.jp/akiba...mage/nx2d2.jpg

@STEvil

so BP is venice with rev E3 and BW is venice with rev E6 right ?

BV is used for Manchester (2 x 512K L2)
CD is used for Toledo (2 x 1MB L2)

And, BTW, clearly, AMD is not going to use 2 x 1MB L2 die for Venice (1 x 512K L2) parts.

So, more than 1 die (cache size, etc) can use the same "E6" stepping.

For a while I thought AMD was using the #s just to differentiate dies, with E3, E4 and E6 all being the same "E" stepping, but if this email is correct, that is clearly not the case.
06-09-2005, 11:43 AM
_Eduard_

I can't wait for E6 sempr0ns :D
06-09-2005, 12:10 PM
Quanticles

Quote:

Originally Posted by Davos

e3 can also be written as 3e

3e + 3e = 6e :)

but if it was e³ + e³ then it would be 2e³ :D

:off: soz

e3 is a variable name though, you cant have it start with a number =P
06-09-2005, 01:21 PM
s7e9h3n

Quote:

Originally Posted by setyotomo

@s7e9v3n : 9476 PC Marks :banana:

That's not my work, it's OPB's with the cpu he got from me... ;)
06-09-2005, 03:07 PM
dimasdw

Quote:

Originally Posted by eva2000

:slobber: :slobber: :slobber:

That yours ? :)

no,thats picture from a Hardware website :D
06-09-2005, 03:31 PM
dimasdw

Quote:

Originally Posted by terrace215

BV is used for Manchester (2 x 512K L2)
CD is used for Toledo (2 x 1MB L2)

oh sory I am Wrong,your right ....
I forgot where i read about denmark and Toledo

Link
<translate with http://world.altavista.com/babelfish/tr> :D
06-09-2005, 05:56 PM
Borgschulze

Quote:

Originally Posted by s7e9h3n

Then what's BV? BTW, I think TULLY would be appropriate ;)

Hey, how about we call them...
TOLEDO!
06-09-2005, 09:17 PM
CNCL

Wait, I am lost. Is the new E6 venice/SD core?
06-09-2005, 10:03 PM
OC Detective

As stated the dual core E6 which only has 512Kb of L2 cache per core is called Manchester so any nickname of the E6 single core with only 512Kb of L2 cache should be derived from that and not Toledo.
06-09-2005, 10:04 PM
TMM

Could just be a minor core revision...
:stick:
like the Clawhammer C0 and CG...

Maybe the Venices (if E6 = Venice) will finally have a decent Mem controller :toast:
06-10-2005, 12:42 AM
Fairydust

Quote:

Originally Posted by OC Detective

As stated the dual core E6 which only has 512Kb of L2 cache per core is called Manchester so any nickname of the E6 single core with only 512Kb of L2 cache should be derived from that and not Toledo.

Correct me if I am wrong, but according to AMD, the 1 Mb version is the E6 and the 512 Kb is the E4
06-10-2005, 12:53 AM
Lithan

Quote:

Originally Posted by dimasdw

BP is venice and what is BW ?
maybe we can call Toledo, TODO or TOLE :D

Bout time someone got it right.

Let my provlaimation go across the land!
They wil be known as Todos!
06-10-2005, 01:05 AM
Fairydust

But teddies are cute and fluffy. Todos are mean and smelly. so we got Todos, Tully and Teddy now?
06-10-2005, 01:17 AM
AgentVX

Quote:

Originally Posted by OC Detective

As stated the dual core E6 which only has 512Kb of L2 cache per core is called Manchester so any nickname of the E6 single core with only 512Kb of L2 cache should be derived from that and not Toledo.

Then we should call the dual core one Man United and the single core one will be Man City :ROTF:
(English football joke)
06-10-2005, 01:22 AM
shuRe

winchester = winny

san diego = sandy

toledo = toley, or TROLLEY :cheer:
06-10-2005, 08:04 AM
The Coolest

The AMD K8 0.13µm Hammers were SH7-B3, SH7-C0, SH7-CG, there was also a DH7-CG.
the SH7s were Sledgehammers and Clawhammers, the DH7 was a NewCastle.
The first gen of AMD's K8 0.09µm Hammers were DH8-D0 and SH8-D0.
SH = 1MB
DH = 512KB
7 = 0.13µm
8 = 0.09µm
9 = 0.09µm Dual Core
Its very confusing lately as AMD isn't saying what type any of the E stepping hammers are.
But I'm guessing that the new E6 sempron is going to be a DH8-E6, the current Dual cores are *probably* DH9-E4 for DC 2x512KB and SH9-E6 for 1x1MB

Show 100 post(s) from this thread on one page