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no numa then... hmmm so multiple cpus with numa is still faster than a dual core cpu... but not very much.Quote:
Hi Sascha
for the Dual Opteron I've used a Abit SU-2S motherboard; NUMA was disabled, with ECC Registered memory (ECC off during benchmarking)
so from this we can conclude that the a64 architecture scales very nicely with more bandwidth, wich all tweakers know already :D
Where are the benchmarks though? :(
Perkam
?cant you see them?
he only ran cinebench from what i can see...
For gaming i dont think we will see a big improvement.
we need to wait and see.
well unreal3 and the game engine that splinter cell3 is based on claim to have multi threadding support, but we will see how much of an impact this will have...
rather minimal i think as well...
amd told me that this is exactly why they will launch the dual core chips for the server market mainly, and the desktop dual core chips will only be an addition to the current lineup and will not replace the singe core cpus, like intel plans to do... intel plans to replace all their higher end single core cpus with dual core cpus... we will see if it works out as their dual core cpus come clocked quite a bit lower...
but intel is pushing 65nm really hard, and we might actually see their new 65nm dual core chip codenamed pressler in q3 of this year! so dual core 90nm amd cpus might have to compete with 65nm dual core pressler cpus... wich will def be a much more interesting match than 90nm dual core a64s versus 90nm dual core prescotts :D
No, the reason for the move from s754 to s939 was "dual channel". nothing to do with dual core. Dual core just so happens to conveniently work on the same socket because each processor (single core, 2 cores, whatever) gets 3 hypertransport links to use as it wishes.Quote:
Originally Posted by Jrocket
For all: I have a datasheet on Dual Core Athlon 64 processor and its official name is "AMD Athlon 64 X2 Dual Core Processor".
X2? or x² ? :D
Atleast they are using a name that actually relates to it being a Dual core processor (X2 that is). No stupid "AMD Athlon 64 Hyper Extreme++" names. :)Quote:
Originally Posted by VVJ
FYI... architecture:
http://img8.exs.cx/img8/6210/dualcore7nc.png
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Originally Posted by AMD statement
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Originally Posted by AMD statement
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Originally Posted by AMD statement
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Where did you get that image EMC2? It has also been stated that one of the HT links is used to link the cores IIRC..
aye stevil that is correct at least for 2+ way systems, not sure about between each core on a dual core though as i havent seen anything about it that i can remember anyways :)
dX, yeah! I absolutely agree with you! :toast:Quote:
Originally Posted by dX.
Can we see it?Quote:
Originally Posted by VVJ
--- Stevil ---
I started to say "found it under a green and white rabbit in a hat"... look at the color scheme on the pic ;)
Oh, and the HT link is only used for connection between two physically seperate CPUs, whether single or dual core... read the 3rd quote again closely.
Peace bro
karelke have you signed a non-disclosure agreement? If yes, please read it again more attentively!
I explained this a while ago in the dual core thread. Dual core hammer doesn't use HT for intercore communication, just external. Everything internal is through the SRQ, which can be routed to either the memory controller or the HT links if needed. Thats why S939 dual core chips can have only one HT link for 2 cores (IIRC, could be wrong on that detail), and why they work in existing motherboards.Quote:
Originally Posted by STEvil
Sounds an awefull lot like one of the HT links is being used.Quote:
read the 3rd quote again closely
Two processors combined have 6 HT links total, utilizing one each to connect to each other leaves 4. Those two are used for system (one each?) and memory access (one each?). Now I am not exactly sure on the details, but knowing each physically seperate CPU (ie: different sockets) must have a system and memory link this is how it logically plays out.Quote:
I explained this a while ago in the dual core thread. Dual core hammer doesn't use HT for intercore communication, just external. Everything internal is through the SRQ, which can be routed to either the memory controller or the HT links if needed. Thats why S939 dual core chips can have only one HT link for 2 cores (IIRC, could be wrong on that detail), and why they work in existing motherboards.
Moving two cores onto one die doesnt change the rules that the cores need to talk to each other, and the HT bus is there to do it. What the 4 extra HT links are utilized for (or are they pooled so one cpu can access sytem while another can access more ram?) has not been told to us as far as I know and since the cores can talk to each other the pooling of the HT links to allow one cpu to utilize double the HT links at any given time (where appropriate) does seem the logical way to do things..
Although doing things logically or efficiently isnt in the vocabulary of some.
--- Stevil ---
The key I was trying to draw your attention to in the 3rd quote was, "Directly connects the two processor cores on to a single die to even further reduce latencies between processors"... latency is reduced because they are no longer communicating with each other thru HTT links ;) In the dual-core the HTT links are not used to connected the two cores. The HTT links & the memory controller/interface are shared by the two cores via the crossbar switch, and are not part of the cores "proper".
Another way to look at it is the mem controller and the HTT links are an embedded NB, with the system request interface and crossbar switch the connection between the core(s) and this "internal NB". Also note that thru the use of crossbar technology in the interface, it will be possible for one core to access memory while the other is communicating via an HTT link to the rest of the system or another physical CPU.
Regarding crossbar switches... they allow the direct connection between all devices connected and multiple connections to be concurrent. Example: Core1<->Mem, Core2<->HTT0, HTT1<->HTT2, all at once... or any other combination.
ooops... time for work, later bro :toast:
thx for the infos! :) very interesting... :D
one thing i didnt get though is what the 3 ht links are supposed to be for. on the image it looks as if the memory controller is independant of the 3 ht links, so theres the memory controller AND 3 ht links?
then what are the 3 ht links used for? is this drawing showing an 8xx dual core cpu?
because 1 cpu only needs on ht link to connect the cpu to the system.
2 cpus use 1 to connect to the system and one to connect to the other cpu, right?
and 4 or 8 cpus use the third ht link to connect to yet another cpu, building up a ht link network between the cpus so to say.
please correct me if im wrong :D
so in an 8way system each cpu uses 2 ht links to connect itself to the other cpus, and one to connect itself to the system? but does this mean we have 8 cpus hooked up to 1 chipset on an 8 way system? or 2 chipsets or even more?
does anybody know how it works on the nf4 pro chipset?
1 master chipset (2200) hooked up to one cpu and then 1 slave chipset (2050) hooked up to the other cpus? are the master and slave nf4 chipsets connected via the cpus ht links or are they hooked up with their own ht links somehow? or pciE links maybe? :confused:
only the opteron level of cpu will feature 3 active ht links. currently, the a64 has one link active, the FX two, and the opteron 3. one of the three available is used to interconnect cpu's in the opteron line. this is needed becasue they are not in the same package.
the SRI and crossbar manage the communications between the processors. in dualcores.
I assume the 3 HT links are need to be able to handle the bandwidth demand of a dualcore...2 cores means twice the processing power, and double the info. only 2 links would only be equal to the FX line now, so three is needed to see the real performance boost.
As far as i know, there can be up to a max of 16 or 24 HTT lanes in current standards, but i would have to check the pdf again.
well the direct connection between cpus is certainly not NEEDED, they could also be connected via the chipset, wich would be much much slower, but yeah i get your point :D
and are you sure the fx has 2 active links? for what? :confused:
i think your mixing things up there, current single core opterons also have 3 ht links, just like the to be anounced dual core opterons, at least afaik.
that's what i am saying...currently they have these links. this will not change with the dualcores, as they will fit in the same sockets...on the same boards. the way it's implemented, and the similarities to what we have currently, is highly intentional. that's why we have the crossbar controller, as doing it any other way WOULD require a new pinout...like the M2 socket, or whatever it's called, ot the 1066pin amd socket(dunno 'bout that one. may have just been an early revision of these cores or something).
the a64 has one htt lane, which is bi-directional. 16bit, 2-way.
the FX have 2 dedicated lanes 16-bit one-way, although from what i understand, thay can be two-way, but i don't know for sure.
With the FX having dedicated lanes, this increases the overall possible bandwidth of the chip by huge ammounts...rather than 22.8gb switched bi-directional, it's 45.6gb possible. These seem like large numers, but the chipset has to support a multipler to get to the upper reaches...2000mhz on nforce4 is = to what, 20.0gb? easier for the FX to utilize the most of this bandwidth, because of the 2 lanes.
The opteron uses the third lane to connect to the second cpu, and only differs from the fx in this way. managing all the communcations explain the slight drop in performance from FX to opteron.
anyways, even the FX and opteron, limited by chipset as they are, are not using most of this bandwidth. so it makes sense to just drop in another core to make use of all that extra, and even though the crossbar is there, adding latency, keeping the 2 active lanes means that the small amt of latency should not matter, if you go to two lanes bi-directional, OR dedicated.
your saying the a64 has 1 ht link for up and downstream while the fx has one dedicated ht link for up and one for down? :confused:Quote:
Originally Posted by cadaveca
and the performence difference between an opteron and an fx has to do with what? the opteron having to handle the system communication while the fx doesnt? sorry, i know thats not what your trying to explain, but i dont get it, lol :D