AMD Server Roadmap 2010-2013 : 10C/20C 28 nm ???

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Originally Posted by mattkosem

A 25% shrink (32² vs 28²) is a fairly sizeable jump, no? All things held constant, that should cut power consumption and heat down by ~25%. It's not more than half like the jump to 22nm, but it's definitely something.

--Matt

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that's is not a real measurement though. the width of a transistor gate is not the same as the length and is changed depending on how faster the transistor needs to be. also, it's common to see larger than feature size transistors on a new process.

you might want to check out these numbers on more important measurements such as contacted gate pitch (minimum distance between two gates) or SRAM cell size.
http://www.realworldtech.com/page.cf...109003617&p=11

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Originally Posted by BoredByLife

28nm is considered a half-node process. It is easy to implement without changing your designs on 32nm. I dont know if you have any backgrond in IC design? But it takes a lot of time and is very complicated. Especially when designing a processor. If you can just use a better process without changing the desing much, you win time, money and performance. I don't see anything bad about it.

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a smaller node does not mean faster. all kinds of effects explained by quantum physics that were previously negligible cause many problems at sub 90nm.
rushing to a new node won't provide faster performance especially considering just how much labor goes into their current physical designs. many of the circuits are fast because they are custom made to reach timings. i guess it's kind of like starting weightwatchers to get washboard abs but you sit on the couch and watch tv all day. you have to put some work into it. examples of this could be fermi or r600. they were on cutting edge nodes but sucked because of who made them.

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Originally Posted by Chumbucket843

that's is not a real measurement though. the width of a transistor gate is not the same as the length and is changed depending on how faster the transistor needs to be. also, it's common to see larger than feature size transistors on a new process.

you might want to check out these numbers on more important measurements such as contacted gate pitch (minimum distance between two gates) or SRAM cell size.
http://www.realworldtech.com/page.cf...109003617&p=11

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Nice read, thanks for the info. It looks like it's not quite as big of a jump (provided those SRAM numbers translate to CPUs 1:1) - more like 10% difference in overall transistor dimensions, correct? Seems like TSMC kind of dropped the ball somewhere along the way though, since the drive strength seems to have only dropped by only a couple/few percent.

--Matt

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Originally Posted by Chumbucket843

that's is not a real measurement though. the width of a transistor gate is not the same as the length and is changed depending on how faster the transistor needs to be. also, it's common to see larger than feature size transistors on a new process.

you might want to check out these numbers on more important measurements such as contacted gate pitch (minimum distance between two gates) or SRAM cell size.
http://www.realworldtech.com/page.cf...109003617&p=11

a smaller node does not mean faster. all kinds of effects explained by quantum physics that were previously negligible cause many problems at sub 90nm.
rushing to a new node won't provide faster performance especially considering just how much labor goes into their current physical designs. many of the circuits are fast because they are custom made to reach timings. i guess it's kind of like starting weightwatchers to get washboard abs but you sit on the couch and watch tv all day. you have to put some work into it. examples of this could be fermi or r600. they were on cutting edge nodes but sucked because of who made them.

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It not a smaller node, its a smaller HALF-node. You don't have a lot of work if you want to change your desing to a half-node. And smaller means faster. Anybody knows that. The problem you get is leakage. But the performance will always be better on a smaller (half)node.

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Originally Posted by mattkosem

Nice read, thanks for the info. It looks like it's not quite as big of a jump (provided those SRAM numbers translate to CPUs 1:1) - more like 10% difference in overall transistor dimensions, correct? Seems like TSMC kind of dropped the ball somewhere along the way though, since the drive strength seems to have only dropped by only a couple/few percent.

--Matt

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SRAM numbers translate fairly well especially if it doesn't need to be ultrafast. yeah, 10% smaller sounds right. how a 28nm BD would take advantage of that is another topic though.

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Originally Posted by BoredByLife

It not a smaller node, its a smaller HALF-node. You don't have a lot of work if you want to change your desing to a half-node. And smaller means faster. Anybody knows that. The problem you get is leakage. But the performance will always be better on a smaller (half)node.

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you don't have to do as much work to get a *working* chip. making it fast requires custom design which is a lot of work.

smaller does not mean faster. if that were true why would anyone research or implement hkmg, 3d transistors, or nanomaterials? all of the research would be on lithography.

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Originally Posted by Chumbucket843

smaller does not mean faster. if that were true why would anyone research or implement hkmg, 3d transistors, or nanomaterials? all of the research would be on lithography.

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You do realize HKMG and 3D transistors are needed for reducing the Gate leakage current right? The industry didn't want high-k, it needed it because the SiO2 barrier was becoming so thing. High-k even lowers the performance, it reduces channel mobility.

You also do realize the drain current formula has a W/L dependency? So reducing L gives you higher performance?

yeah, but leakage is backing up my point. you can make it smaller but leakage will negate any benefits of it.

btw, you need high gate capacitance to attract a big charge to the channel so you need high C-ox, thus a need for hiK. the more charge you attract, the higher I-ds goes.

http://www.intel.com/technology/silicon/HighK.pdf

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Finally,
we showed that high-k /metal–gate CMOS transistors with the
expected high drive currents can be experimentally achieved
by using metal–gate electrodes with n+ and p+ work functions
1) to provide the right threshold voltages and 2) to improve
the channel mobilities for both the n-channel and p-channel
MOSFETs. The improvement in drive currents is due to the
scaling of inversion electrical gate oxide thickness and increase
in channel inversion charge. We believe that this is a very
important exercise because it shows that very high-performance
high-k CMOS transistors can be experimentally achieved with
the use of metal–gate electrodes on high- gate dielectric.

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Quote:

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Originally Posted by Chumbucket843

SRAM numbers translate fairly well especially if it doesn't need to be ultrafast. yeah, 10% smaller sounds right. how a 28nm BD would take advantage of that is another topic though.

you don't have to do as much work to get a *working* chip. making it fast requires custom design which is a lot of work.

smaller does not mean faster. if that were true why would anyone research or implement hkmg, 3d transistors, or nanomaterials? all of the research would be on lithography.

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More research into lithography is not going to help. That is why they are looking at these things.

Quote:

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Originally Posted by Chumbucket843

yeah, but leakage is backing up my point. you can make it smaller but leakage will negate any benefits of it.

btw, you need high gate capacitance to attract a big charge to the channel so you need high C-ox, thus a need for hiK. the more charge you attract, the higher I-ds goes.

http://www.intel.com/technology/silicon/HighK.pdf

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You do realize you just proved my point right? In my previous post I said performance is better with smaller L. No matter what, but leakage becomes a problem. Performance and leakage arent related...
You dont need high C-Ox, you need the same one for every generation. That is why the gate dielectric grows thinner and thinner to maintain this same value of C-OX. And because leakage became a problem with a SiO2 layer smaller then 2nm, they had to put in high-k materials, and because poly silicon doesnt go well with that they changed it to metal gates....
Just look some things up before you start babbling nonsense again please.