Fudd: Nehalem 3.2GHz goes up to 4.5GHz on air

I love the memory score comment... useless info here, move along.

I really can't wait for Nehalem. If everything is to be believed it will be perfect for an upgrade (from my 4800+). Hopefully it will be a 'tock' like Conroe was.

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Now, Intel has decided to unlock memory ratio adjustments on Core i7 920 (2.66 GHz) and 940 (2.93 GHz) SKUs too, thus opening the memory playing field for all and sundry.

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It is claimed however, that 'overclocking' the QPI speed will only realise small performance benefits, yet the adoption of what is effectively an unlocked memory controller, will give enthusiasts that little more freedom to experiment and attain the best that the Nehalem platform has to offer.

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http://www.tweaktown.com/news/10179/...king_friendly/

Looking forward to seeing what this memory controller can do. . Wouldn't it be nice to just dial in a dram speed without worrying about dividers like the way it is now with the fsb?

I know this is XS forums, but LN2 seems to be a bit over-rated. It's just that even the most Xtreme of all the enthusiasts still does not use LN2 for anything else other than an enthusiast sports car driver would use a drag racer down the quarter-mile.

Excuse me--this was my first time making such a comment here on XS forums---hopefully I do not get banned for saying this! :P

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Originally Posted by Blauhung

just to clarify, there is no E0 stepping. D is as high as it's gotten

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OK, i thought they had gotten to E. The one I am referring to is a C1 or C0 (can't remember off the top of my head). How are the D's looking? Is D going to be the release stepping?

Memory bandwidth is going to be incredible with Nehalem. Not really looking forward to too much else with this architecture.

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Originally Posted by Booj

Looking forward to seeing what this memory controller can do. . Wouldn't it be nice to just dial in a dram speed without worrying about dividers like the way it is now with the fsb?

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Don't get excited :) memory dividers are pretty much standard for issuing the clock to the memory, unless Intel has decoupled the memory clock from the system clock to let it float. The only efficient way to clock the memory correctly is to use dividers where are some preset incremental step to synchronize clocks.

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Originally Posted by JumpingJack

Don't get excited :) memory dividers are pretty much standard for issuing the clock to the memory, unless Intel has decoupled the memory clock from the system clock to let it float. The only efficient way to clock the memory correctly is to use dividers where are some preset incremental step to synchronize clocks.

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Yeah wishful thinking I know, but as far as I know ATI did it with the RD600 chipset albeit with the fsb, so it has been possible.. Perhaps it had a much finer range of dividers to give the appearance of unlinked memory. Mind you that chipset didn't turn out too well did it..