Intel Yorkfield/Wolfdale new steppings

damn it i just bought an e8400:( it should be here this week.

Both my q9300`s are stepping 7 revision M1, whats the newest revision/stepping on those?

I wonder when they'll come up with a power state designated "C0M4" - a power state so deep that once the chip enters C0M4 there's no way to tell if it'll ever recover.
http://largon.wippiespace.com/smilies/lol.gif

So what do the experts say? When you look at the spect's, is it worth it to step up to a "New" E3110 form an "Old"?

Or are the changes so minor that noone will ever notice what rev. they have?

I'll help clear this mud up a bit.

C and E steppings refer to the Penryn product with 6MB of cache.

M and R steppings refer to the Wolfdale product with 3MB of cache.

The changes from C --> E and M -->R are equivalent and are pretty much the same changes just on the 2 different products.

Revision changes are done most of the time to iron out bugs and make manufacturability changes that lead to higher yields and better binning flexibility.

The stepping change was done to add in some features that have been developed but weren't quite ready at release time of the original design.

hi mate

what can overclockers expect from these new steppings

are they addressing any FSB related "issues" :D

i know intel probably doesn't give much of a hoot but worth asking hahah as i remember how good some of the 65nm revisions were but we may not be there just yet to have that G0 type revision just yet :)

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Originally Posted by dinos22

hi mate

what can overclockers expect from these new steppings

are they addressing any FSB related "issues" :D

i know intel probably doesn't give much of a hoot but worth asking hahah as i remember how good some of the 65nm revisions were but we may not be there just yet to have that G0 type revision just yet :)

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I think I saw something that might help with MCM'd yorkies FSB stability in C-3 which probably got ported to E as well, but I really have no clue:p:

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Originally Posted by Blauhung

I think I saw something that might help with MCM'd yorkies FSB stability in C-3 which probably got ported to E as well, but I really have no clue:p:

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I've also noticed that P45 chipset helps quads with FSB

the real interest to me is dual cores as high MHz particularly after some new technologies are coming out and porting some very intensive workload go to GPU where they are more efficient such as video encoding & most older benchmarks are still more efficient with high FSB dual cores

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Originally Posted by Monkeywoman

does this mean that these are slightly faster?

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Not really. only if the code actually uses those instructions, which is very unlikey except in certain special apps, which I think aren't so mainstream. ;)

Quote:

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Originally Posted by Blauhung

I'll help clear this mud up a bit.

C and E steppings refer to the Penryn product with 6MB of cache.

M and R steppings refer to the Wolfdale product with 3MB of cache.

The changes from C --> E and M -->R are equivalent and are pretty much the same changes just on the 2 different products.

Revision changes are done most of the time to iron out bugs and make manufacturability changes that lead to higher yields and better binning flexibility.

The stepping change was done to add in some features that have been developed but weren't quite ready at release time of the original design.

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I'd meant to thank you for this info:up:

Which of the following feature are already implemented on C1 stepping quad core chips such as the Q9450?:
Description of Change to the Customer:
The Intel® Core™2 Duo Processor E8500, E8400 and Dual-Core Intel® Xeon® Processor E3110 will
undergo the following changes for the C-0 to E-0 stepping conversion:
• New SSpec and MM numbers for the converting products
• CPUID will change from 0x10676 to 0x1067A
• Power Status Indicator (PSI) is supported
• PECI implementation change
• New instructions added – XSAVE/XRSTOR
o New ISA extension for save/restoring context of x87, SSE, and future processor state
• New feature added - ACNT2
o Improved mechanism for determining processor utilization. To be used for more efficient
P-state determination.
• Package change to Halide free package

Reason i ask this is that i see Gigabyte have implemented the C2E/C4 power stats in there P45 bios, in addition they state that:

"Dynamic Energy Saver Advanced
GIGABYTE Dynamic Energy Saver Advanced provides better energy saving capabilities and enhanced system performance. GIGABYTE Dynamic Energy Saver Advanced is the world’s only motherboard energy saving technology with hardware-based Dynamic 6-Gear* Switching. With support for VRD 11.1, GIGABYTE’s DES Advanced allows the motherboard to switch to 1 Gear phase switching during idle, allowing for a dramatic increase in power savings.

GIGABYTE has also retooled Dynamic Energy Saver to allow overclockers to experience the benefits of multi-gear power phase switching while overclocking, providing ultra stable, ultra smooth overclocking performance.
* The 6-Gear feature may vary by model. Gear 1 phase switching requires 45nm processors with PSI signal enabled."

So my question is does the Q9450 have this PSI signal enabled?

E-step conversion is happening on most of the current C-stepping Yorkfield processors sometime in mid Q3, per my contact @ Intel.

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Originally Posted by TankGuys

E-step conversion is happening on most of the current C-stepping Yorkfield processors sometime in mid Q3, per my contact @ Intel.

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Does that mean Wolfdale is later Q3 or Q4?

Thanks