not sure if anyone said this or not,,
ok i just deleted what i said as i was way off base, kind of.
here is what the Intel 965 Chipset PDF says
so.... looks like the HECI is going to have a direct relationship on the Northbridge.Quote:
Note: As HECI is an internal device in the GMCH, the INTA# pin is
implemented as an INTA# message to the ICH8.
so has anyone tested disabling those settings and then checked for stability. and such.
interesting that those settings would even show up... Alot of the HECI talk in the PDF is all memory mapping, so its hard to say what the true nature of HECI is without having someone who knows ALOT about the intel chipsets.
*EDIT*
further reading is indicating that the HECI is a host controller, which directly interacts with DMA and the processor.
There is talk about power states of DMA devices, memory mapping of DMA devices and other things of that nature.
this could be some sort of power state setting, which probably wouldnt have any effect on system stability when certain power saving features arent being used. S1/S3 mode ? C1/EIST ?
hard to say..
but interesting that it shows up when the fan controls are set a certain way