well we know none of this for sure , but time will tellQuote:
Originally Posted by onewingedangel
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well we know none of this for sure , but time will tellQuote:
Originally Posted by onewingedangel
umm how many times does it have to be said 40% more speed isn't 40% more performance.Quote:
Originally Posted by onewingedangel
It's not a truly linear increase, but performance does scale almost linearly with clocks assuming there aren't any IO bottlenecks. The extra cache (50% extra) should mean that the FSB is no more of a bottleneck than at present, so any bottlenecks would be those of the execution core itself, but compared to conroe they will still feature the same percentage of branch misses etc, they'll just get through the cycles quicker.
They will NEVER be able to scale that thing so hihg right away with 45nm, which is probably because of the power comsumption. The QX6700 is at 125W TDP and uses the full wattage of it, it just sucks if you look at the power it draws (so does AMD's FX's, but they're old) if they make 45nm parts with a voltage of 1.2 or 1.15 and clock it 40% higher, that would make for another 15-20% increase in TDP. I highly doubt they would be so stupid to realease a 150W TDP product... AMD though is stating that their Q-core will have a 95W TDP which is quite nice... let's just hope they keep each other going!!! :toast:Quote:
Originally Posted by onewingedangel
Whenever I see POS, I think "Point of Sale", which in this case doesn't make sense. For shame.
a 3.66ghz part (333x11) should be doable within current TDP's, possibly even a 3.8ghz part(intel will be able to use half multi's with their 45nm chips, to help remove the huge difference in clockspeed throughout the range whilst maintaining the same ammount of sku's). With selective binning it would probably be possible on the 65nm process. A 4ghz part is not outside the realms of possibility for the 45nm process. It all depends on how tightly intel want to bin (look at amd's current 3ghz parts to see just how much you can push the binning process if need be).Quote:
Originally Posted by josty2
Not to mention the potential overclocking (with the associated increase in TDP).
AMD saying that they will be 40% better than cloverton (in some applications) more than likely means they will remain semi-competitive, but certainly doesn't mean k8l will be the better product, in fact I'd argue the opposite. BUt until we have these chips in our hands and have some conclusive benches this is all idle speculation.
Does journey consistency constraints ring a bell, too?Quote:
Originally Posted by Growly
I'm not saying that 45nm will clock 40% better than 65nm - there are still huge reserves in the 65nm process, but intel aren't tapping into them. Two of the main reasons are firstly not to fragment their product range by having core2's that range greatly far too greatly in power (which the half multi's will help - allows core clock differences of 166mhz when using a 1333fsb, so the market can be positioned more like merom with smaller jumps in performance when moving up the sku's) and secondly there is no need to strictly bin the products when they already handily outperform amd when they don't raise the clocks (which k8l will help with). Intel have announced they plan to clock the 45nm core2 in the 3.6-4ghz range, so they clearly have the intention of moving core clocks higher across the range.
The 45nm chips could be clocked 40% higher than the 65nm chips, in part because of the process, and in part because of greater competition between the two big cpu companies encouraging stricter performance binning.
Intel is adopting a better fsb, by using Nehalem architecture no? "The chip will have 8MB of shared L2 cache, simultaneous multi-threading (the ability to execute two threads per core,) support for Intel's Common System Interface, and an integrated memory controller." Just have to wait until 2008?Quote:
Originally Posted by brentpresley
I can't believe you mentioned C2Q and QFX in the same sentence when speaking of power consumption.Quote:
Originally Posted by josty2
http://www.lostcircuits.com/cpu/amd_quadfx/prime952.gif
IMO it's every bit as likely that C2Q will clock 40% higher on 45nm process with 100% performance scaling as it is that Barcelona will be 40% faster than C2Q clock for clock. ;)
BTW, where did you get 95W from? Barcelona has a TDP of 125W at some as yet undisclosed clock speed. Are you talking about AMD's 45nm quads, dual core Altairs or some lower clocked EE versions?
http://www.hkepc.com/bbs/itnews.php?tid=709944Quote:
Originally Posted by LOE
2.5GHz is the latest number.
don't bother trying to reason with him: He's so far lost into believing everything he hears from fanboys at AMDzone that he won't listen. For the last time, AMD talking about 40% preformance increase is worse than useless as news, because no third party has done a benchmark. AMD's idea of a demonstration is TASKMANAGER, for crying out loud! When I see an Xbitlabs review of K8L, I'll believe that. same for penryn. I hear a lot of claims about preformance from different manufactures, and so far, they are about half as reliable as the inq.Quote:
Originally Posted by red
Everyone Hyped up conroe before it's launch because there were leaked benches, and AMD knows this. IMHO, since I don't beleive AMD is stupid, I think that either A) they don't have ES chips yet, which is bad news, or B) Barcelona isn't QUITE at the intel C2Q+40% mark just yet. Time will tell
Agreed, its all hot air but I really hope there is some truth though the big question is how well will it scale ???, I very much doubt as well as C2D going by previous efforts :fact:
Straight from the horse's mouth: K8L will be out this Summer. July I presume.Quote:
Originally Posted by Hector Ruiz
rumors say Barcelona will be in the streets by May (or mid April if things go well).Quote:
Originally Posted by lapdog
Randy Allen confirms(yet again) the April-May time froame for Barcelona's arrival!
http://blogs.business2.com/utilitybe...rimming_w.htmlQuote:
AMD (AMD) remains confident that the quad-core Barcelona chip for enterprise servers, due at the middle of this year, will deliver a 40 percent performance boost over what's available today – an advantage Intel (INTC) won't be able to match.
I had lunch on Tuesday with Randy Allen, AMD's corporate vice president for servers and workstations, and had a wide-ranging talk about the status of AMD's server business and competition with Intel. Undeterred by the disappointing financial results AMD announced that day, Allen made some bold statements about the company's upcoming quad-core server chip. Here are some key points from our conversation:
* AMD gains in 2006 chip rankings
* AMD will begin shopping the Barcelona chip around to customers in the April-June time frame (so, in about three months).
* Allen thinks Barcelona's advances in virtualization and power management (and other technologies) are so significant that to compete, Intel will have to significantly change its front side bus or micro-architecture – no simple task.
* AMD decided two years ago to pursue the current Barcelona strategy, even though it would take six months longer than other options and Intel would almost surely come to market with a quad-core product first. (Intel did, with Clovertown.) AMD believes its quad-core Barcelona design is far more efficient, and that customers will notice.
* AMD is hopeful that customers are holding off on purchasing Intel's quad-core product, released in November, based on the fact that Intel didn't say much about it in its most recent earnings call. Yesterday, however, CNET quoted a Mercury Research analyst saying Intel's Clovertown chip is already contributing a meaningful amount of business to Intel.
* Allen said Q4 2007 will be when the first real impact of Barcelona comes through in AMD's financial statements. I noted that if the chip does well, it will provide very flattering comparable sales figures to the Q4 results AMD announced this week, which were short of Wall Street's expectations.
* Barcelona will have healthy margins, Allen predicted – AMD seems confident that because it will provide such a performance advantage over Intel, price competition won't be as intense.
* While he doesn't expect customer uptake to be as quick as the shift from single- to dual-core, Allen said because AMD has made it easy for customers to drop the quad-core solution into their existing equipment, customer acceptance will be rapid and broad-based.
* Allen downplayed the significance of Intel's partnership announcement with Sun Microsystems (SUNW) on Monday. Though he admitted that AMD liked being Sun's exclusive provider of x86 chips, he said it seemed to him that the partnership was more about getting Intel to back Solaris than it was about selling a whole lot of servers. He also said this doesn't mean AMD won't still see Sun as a great customer.
My take: Chip makers are, without exception, confident about their upcoming products – so I take everything Allen said with a grain of salt. Still, Allen laid down some very specific claims and projections, particularly the 40 percent performance boost. (When I pressed him on what exactly that 40 percent includes, it was slightly less clear; he mentioned a number of metrics, including performance per watt.)
* The future of password security: no easy answers
Also, it is obviously in AMD's interest to drum up customer curiosity about Barcelona, in hopes that some will hold off on purchasing Intel's quad-core offering, and at least do an Intel/AMD bake-off later this year.
Is Allen's confidence in Barcelona warranted, or is it an attempt to spread anti-Intel FUD (fear, uncertainty and doubt)? Time will tell.
I guess this won't be enough for some so tehy will say it is probably April-June of 2008 :D.Oh well... :)
I agree AMD are no fools ;), they have to get that chip out ASAP...Quote:
Originally Posted by LOE
Randy Allen,AMD's corporate vice president for server and workstation products said: "We expect across a wide variety of workloads for Barcelona to outperform Clovertown by 40 percent."Quote:
Originally Posted by LOE
1. I can't find the "UP TO" part in Allen's statement.
2. "wide variety" doesn't mean "different situations".
How by my logic a 3GHz K8L will perform like a 4.2GHz C2D?Quote:
Originally Posted by LOE
Quote:
Originally Posted by gOJDO
Quote:
Originally Posted by gOJDO
So, what's your problem dude? Are you blind or what?Quote:
Originally Posted by gOJDO
Oh, yeah, you are right.Quote:
Originally Posted by LOE
1-24-2007, 02:52 PMQuote:
Originally Posted by LOE
11-28-2006, 06:42 AMQuote:
Originally Posted by LOE
11-28-2006, 08:05 AMQuote:
Originally Posted by LOE
11-29-2006, 12:54 AMQuote:
Originally Posted by LOE
11-28-2006, 05:42 AMQuote:
Originally Posted by LOE
Ok same thing applies to AMD that we applied to Intel when they were wildly claiming huge performance increases with Conroe in late 2005.
Show us. If you have something to show, show it. "Scheduled" launch dates can change. Both teams do that, but AMD is practically known for announcing on the month of delivery "won't be out for 1-2 quarters more". So I have doubts on the delivery date, not extreme ones because they know they need this chip but doubts because they apparently don't even have samples yet.
So much like Conroe at IDF, show us what you've got. Otherwise the PR stuff doesn't really do much except start discussions like this one...
Where can i find reliable information that 45nm Quad Core Xeon will work @ 4.2 GHz?
I would love to see that info from AMD. Would you like to post a link, please?Quote:
Originally Posted by LOE
I think that you don't know if K8L will have or will not have any bottlenecks.Quote:
You mean kentsfield has no bottleneck?
I would like to learn something more about the Kentsfield bottlenecks. It seems that you are understanding the the "bottleneck" problems very well. Would you be so kind and enlight me about them, please.
So far, I found this article online:
Quote:
Intel zipped up the FSB speed for the Core 2 Quadro to 333 MHz compared with the 266 MHz for Core 2 Duo. Our test results reveal that a FSB1333 (true 333 MHz) does not entail advantages - at least not based on the tests at a CPU clock speed of 2.66 GHz.
http://www.tomshardware.com/2006/09/...age/page4.htmlQuote:
Core 2 micro-architecture offers a few features to ease the strain on memory access, whereby higher FSB or memory speeds barely register any speed advantages.
A second tapeout? :rofl:Quote:
Originally Posted by LOE
http://en.wikipedia.org/wiki/TapeoutQuote:
In electronics, tape-out is the name of the final stage of the design of an integrated circuit such as a microprocessor, the point at which the description of a circuit is sent for manufacture. A modern IC has to go through a long and complex design process before it is ready for tape-out. Many of the steps along the way utilize software tools collectively known as electronic design automation. Tape-out is usually a cause for celebration by everyone who worked on the project, followed by eager anticipation of an actual product returning from the manufacturing facility.
http://www.princeton.edu/~wolf/moder...9-1/img011.GIF
http://www.princeton.edu/~wolf/moder...9-1/sld011.htm
http://www.theregister.co.uk/1999/07/14/what_the_hell/Quote:
Tapeout is a sequence of multiple steps. It indicates when the database that contains the design information is sent to begin the preparation of masks. Masks can be thought of as a template that is used in the semiconductor manufacturing process. Previous the database was a paper tape, which today has been replaced by an electronic carrier.
http://www.cerc.utexas.edu/~jaa/talk...7/index-8.htmlQuote:
When Do You Tapeout? (Motorola criteria)
- 40 billion random cycles without finding a bug
- Directed tests in verification plan are completed
- Source code and/or functional coverage goals are met
- Diminishing bug rate is observed
- A certain date on the calendar is reached
Sorry, but in your links there is no info from AMD!Quote:
Originally Posted by LOE
Quote:
Originally Posted by LOE
Quote:
Originally Posted by LOE
After the tapeout and the production of the first A0 chips, debug folows. In the debug phase, eventual "bugs" are being removed and the integrated circuits are being improved and optimised in more steps(known as stepping). Also, the microcode is usually upgraded(known as Revision).Quote:
Originally Posted by LOE
New tapeout is needed when major architectural changes are going to be made or when transiting to another process node.
K8L was taped out in August and was being debuged. The first "demonstration" was in December with A2 stepping. When the debugging is finished, then the Rev. B1 will be ready for mass producing.
New tapeout requires months, and another few months for the debugging, before it can be mass produced for end users.
None of the links, you've provided is quoting AMD statements. Considering the_INQ as source of information is ridiculous! I'll not waste time, looking after their missleading false articles about ReverseHyperThreading in K8, quadcore K8, 65nm K8 available in august, K8L to come in 2006, etc.Quote:
Originally Posted by LOE
You are talking no sence. Just chechk-out the quotes and the links I've provided about tape-out. Pay attention on the tasks, that have to be done before a tape-out.Quote:
Sometimes bugs in the chip cannot be removed only by optimising the process. That when you make a new tapeout, new mask.
No, I can't. Rev. A is for ES testing purposes only. Rev. B or higher is for mass production and will go on the market.Quote:
Can you post a link about production ready B1 silicone?
you guys are tiresome, seriously.
Oh yeah?Quote:
* While he doesn't expect customer uptake to be as quick as the shift from single- to dual-core, Allen said because AMD has made it easy for customers to drop the quad-core solution into their existing equipment, customer acceptance will be rapid and broad-based.
Such as into my 940 and 939 systems?
That chart is unfair. There is indication that the FX-7x power consumption is actually caused by the chipset on the 4x4 boards, not the CPU itself. Then you wouldn't experience it with the same CPUs in other platforms.Quote:
Originally Posted by Fred_Pohl
Sounds like the first Barcelona ES chips will finally arrive in April-June. How much longer does it usually take to make enough chips for a hard launch?Quote:
Originally Posted by informal
Or do you think that AMD will skip the ES "shopping" phase and go straight into volume production?
Quote:
Originally Posted by uOpt
You would be partially correct if those were system power measurements, but they are not. Those power consumption figures were obtained by isolating the CPU(s) from the rest of the system (including the chipset). As numerous other reviews have already confirmed, an FX74 system draws ~500W with a single <100W vidcard idling compared to ~275W for a QX6700 under the same conditions.
http://www.lostcircuits.com/cpu/amd_quadfx/4.shtml
Power Measurements
Lostcircuits CPU power measurements appear to be very consistent too when you look at FX60, FX62, E6700 and QX6700. FX60 consumes 81W, FX62 consumes 100W and 2x FX74 consumes 266W under XP32. Scaling linearly from FX60 to FX62 we should expect a single FX74 to consume a minimum of 119W x 2 = 238W. However, since we all know that 3Ghz is very close to the limit for K8, we should expect to see power consumption rise exponentially with clock speed when approaching the core's limits. E6700 consumes 54W so logically QX6700 should consume a minimum of 108W and we all know that 2.66GHz is not even close to the limits of 65nm C2Q. It's hardly a perfect testing methodology but I've yet to see any better.Quote:
Looking at system power consumption is interesting to a certain degree, however, for all practical purposes we are more interested in the isolated CPU power consumption. To estimate the latter, we used the same power measurement setup as in previous reports. Briefly, we used a Fluke 80i-410 AC/DC current probe in combination with a Wavetek Meterman 30XR multimeter to measure current through the isolated +12V supply lines feeding into the CPU VRM. To increase granularity of the measurements, we ran the supply lines in a triple loop through the clamp. The clamp itself was calibrated using a BK Precision model 1692, 30V 40 A DC power supply. Since there is a temperature dependency of the probe, we monitored the zero-current offset at the beginning of each measurement as well as at the end of each run. If the values drifted we retook the measurements. Despite these precautions there are possible deviations of the read-out from the real current, however, these errors mostly affect the lower (processor idle) measurements. We estimate that the errors should not be more than 10% at the lower end of the data and less than 5% in the mid and higher data range. Moreover, since the same procedures were applied to all processors tested, there may be an offset in the absolute numbers, however, the relation of the individual cores to each other with respect to power consumption should be fairly accurate. The extremely high power consumption of the CPU at full load causes a voltage droop by approximately 500 mV on the 12V output, the calculations are corrected accordingly.
In addition to the method outlined above, we used a modified PSU to run the 12V line directly through the Wavetek Meterman and read out the current. Both methods gave identical results.
Barcelona cant be this good.
Cities names = mainstream (normal cpus)
Star names = especial CPUs (high end)
expect stunning new from me in minutes :)
Tsk,tsk,tskQuote:
Originally Posted by Fred_Pohl
Those are the final production revisions,NOT ES!
What do you think,that Sun will get quad core ES Barcelona in April and make an uber expensive supercomputer with a bunch of ES chips.You gotta be kidding...
April-June,final shipments of the so called RevB (final production rev.).
ES are probably wandering around in the wild as we speak.But we all know AMD,and this time the NDA curtain reached it's highest peak.Not surprising at all ,if we consider the fact that this chip is the basis for the next 2-3 years of AMD product lineup.
Thanks, Fred_Pohl, I'm glad to see somebody isolated the CPU to verify whether they cause the trouble or not.
I am very sad to see that AMD was willing to sacrifice even the biggest advantage they had over Netburst for this silly 4x4 platform :(
Sorry to burst your bubble,but Barcelona was not named after a city,but after a formula 1 race circuits ;)Quote:
Originally Posted by metro.cl
So is Budapest and Shangai ;).
SO if we follow the logics about the F1 and what it means(uber fast speed cars :D),Barcelona can be that fast :D.And more probably :D.
its appearant that loe doesn't understand much engineering.
after a0 silicon comes back, you will have chances to de/activate some of the dfm redundancies to save your silicon and do some minor adjustments in the stepping.
another tape out would be called revB and so on.
april-june shipments will be a joke. more like sampling. i dont expect k8l to enter volume production for desktops before september. amd doesnt even have enough 65nm capacity yet to support both server and desktops.
exiting 2007, amd should still sell more 90nm am2 chips than 65nm am2 and 65nm k8l combined.
So then you either believe that AMD intends to skip the ES process with Barcelona and go straight into volume production based solely on internal testing or that everyone is scared silly of violating the NDA of little AMD but couldn't care less about violating Intel's NDAs?Quote:
Originally Posted by informal
Does this popular "AMD=TOP SECRET" fanboy myth really make sense to you? AMD hyped K8 for 3 years and the first ES BMs appeared 16 months before the launch yet you believe that K8L will go from vaporware rumors and task manager demos to hard product launch in ~3 months, Good luck with that.
actually AMD's current NDA includes ritual suicide and no I am not joking.Quote:
Originally Posted by Fred_Pohl
First of all,AMD is not a "lil" company anymore:slapass:Quote:
Originally Posted by Fred_Pohl
They have become a large one and it seems that intel fans can't get use to it(and to the fact that AMD now owns one of the largest players in graphics-chip making)
Second,ES are in the wild and people (Charlie D. among them) have the "hard" perf. numbers already(at least in the "Cinebench" league).Charlie confirmed this a few days ago at Ace's.Why the ES don't have a "go" to be early pre-tested by an "enthusiast(s)" is the way AMD wants it to be.
They are floating around,the fact AMD is not "forced" to publish early ES results as they were in the days they had ZERO server and notebook marketshare and declining desktop one,is a no brainer actually(well it maybe is to you...).
You're most welcome, uOpt. I'm glad to see that not everyone goes into instant denial mode when they don't like the facts.Quote:
Originally Posted by uOpt
IMO 4x4 will be much more appealing with 65nm CPU's but it's appeal will still be limited to a small niche in the desktop market.
So Intel published hard numbers, while AMD is saying 40% with no benches. :rolleyes:Quote:
Originally Posted by informal
QFT.Quote:
Originally Posted by HungryForHertz
I too am waiting for New AMD's CPU to be at least just as good as core 2 Duo (i hope they'll be better). I wanna see a constant prices war...
Yeah u know i wanna build a rig with a $100-150 Quad Core CPU :p:
The same goes for ATI/AMD... Nvidia prices are too high.
:rofl:Quote:
Originally Posted by LOE
no but interesting theory :lol:
How could I forget? Since acquiring ATI (on credit), AMD is now so large that they are almost 20% of Intel's size. With their clearly superior products and net income (loss) of -$168M in 2006 to Intel's paltry $5B (profit) it is virtually assured that AMD will continue to grow larger while Intel continues to shrink.Quote:
Originally Posted by informal
I also see your point about AMD not needing any positive press from K8L benchmarks. Considering how competitive their current lineup is and how well their stock is doing for their investors, AMD can well afford to keep K8L's revolutionary performance top secret as long as they wish to. So while Intel is hurriedly demonstrating 45nm Penryns running all manner of real world apps and letting the press actually use them, AMD can afford to sit back and ride the glory wave of their December K8L task manager demo right up to the May hard launch. After all, we all know that AMD could have demonstrated K8L running any app 40% faster than C2 back in December but they simply chose not to. Likewise, final silicon K8L ES chips have been floating about since December but no one would dare to risk the wrath of such a huge corporation by breaking their NDA. Clearly AMD doesn't need to prove to anyone how great K8L is because we already know it is, based on press releases and rumors. I'm sure this all makes perfect sense to you. :rolleyes:
Congratulations on so completely missing the point! :clap:Quote:
Originally Posted by LOE
You guys really act such as if ES are candy and are as common as the morning newspaper and that the big companies are like Oh well just send these to anybody or somebody who will post performance. I hate the whole oh if no es's have been benched yet then they are trying to hide bad performance. NDA's are there for a reason maybe maybe not they are sending out ESs knowing that they will be leaked benchs BUT KEY WORD BUT signing an NDA means you know that you will be sued if you are proved to be the source of information leaking. With those consequences not EVERYONE would be willing to take the chance. So If i don't see any Rev H (which it should be called as AMD is calling it) till the day or day after I wouldn't be surprised because thats how its SUPPOSED to go, Im not going to say they are not going to come out sooner Im just saying stop crying because we haven't seen them yet. And ES's are chips that are being TESTED they can be a performance drop or increase on the final product incase no body remembered this.
wrong:Quote:
Originally Posted by vitaminc
The only major problem with the conversion that really sticks out is that the capacity will be somewhere between 15,000wspm and 20,000wspm. In the current scale of 300mm fabs this is rather small and pushes the breakeven point higher and the available operating margins lower. However, it is more than a stop-gap and the extra capacity, should demand continue to grow will provide sufficient capacity for AMD through 2008
I'm glad that there is so much debate about this. What I make of all this is that both companies are running at Warp 8 to get the perfomance crown. Both are pushing their technologies as far as they can go. So I wouldn't be suprised if it turns out to be a hard to claim an overall winner when you take all data into account.
After looking at all the "data" at hand atm, I think that Penryn will most likely be the chose of the overclocker like C2D is 2day. However the K8L seems to have some nice feats when it comes to power saving and independant IMC/core clocking. So servers builders, silent seekers and low end builders might never leave the AMD plattform. 4X4 is a bad idea today but in three months or so when Agena and the cooler 690 chipset are both on the market, it will probably be the best multi core/gpu platform you can get. Eight cores and all that mem bw + CF should be good when we see more multi core tweaked games on the market.
http://www.overclockers.com/tips01099/
Heh.Quote:
"We expect across a wide variety of workloads for Barcelona to outperform Clovertown by 40 percent."
Note the careful and very specific language used here. Not "in general." Not "most of the time," or "for most apps," or "on average." They win by 40% in a "wide variety of workloads." That's not even a "wide variety of apps," for all we know, it could be just one app!
That was the exact point of the article, that AMD did not clearly state 40% overall better than Clovertown, which a lot of articles are suggesting. That is all. I hope you are wrong too, but you most likely won't be :D
They are not as biased as you think. They do give "pats on the back" to AMD when its warranted. You just feel that way...well cause AMD isn't really upfront about things most of the time. He gave props to AMD for finally admitting that they need to get bigger in order to survive, even though their admittance was forced upon them by an analyst asking a direct question. This article regarding Barcelona being 40% faster without anything specific is just AMD blowing smoke again, so he tells it like it is. No I am not trolling.Quote:
Originally Posted by LOE
The title of this thread certainly suggests it. That's why I agree with uOpt that the thread title should be changed.Quote:
Originally Posted by red
Perhaps something like "AMD: Barcelona to outperform Clovertown by 40% in wide variety of workloads."
cheersQuote:
AMD Quad Core Barcelona Re-Appears
http://img176.imageshack.us/img176/5...celona2fh5.jpg
AMD showed off their native quad core Barcelona processor again and this time round during Windows Vista launch in Japan. The previous appearance is back in November last year where AMD Chief Sales & Marketing Executive Henri Richard did a comparison between Barcelona and Clovertown.
http://img176.imageshack.us/img176/1...rcelonatb5.jpg
http://www.vr-zone.com/index.php?i=4553
Give us the news I'm hoping coming from you we have something interesting the time that has past now, while it can still be measured in minutes, would be many minutes.Quote:
Originally Posted by metro.cl
maybe you can end the flame wars.
what's the rendering score?:DQuote:
Originally Posted by informal
probably somewhere near 70-90% faster clock per clock than K8 and Conroe.Quote:
Originally Posted by Enoc
He hasn't posted any numbers since he said he doesn't want to piss some ppl off :D.But when he gets "a go" ,he will,I am sure.Quote:
Originally Posted by brentpresley
nice...:D , i hope is the other camp he does not want to piss off...:p:Quote:
Originally Posted by informal
Just a tiny clarification: the guy in question(the one i meant) is Charlie Demerjian(from inquirer).
He said at Aces's he has the "hard" numbers on Barcelona,but won't post them since it could cause some problems to his sources.