Originally Posted by back in April
Name: Hans de Vries (hansdevries@chip-architect.com) 4/6/06
ten9 (jhdjksa@huhu.com) on 4/6/06 wrote:
---------------------------
>Hello Hans,
>
>Do you think there is a fourth decoder like Gipsel argues
>here:
>
>
http://www.aceshardware.com/forums/...60237&forumid=1
>
These are the micro-code ep(roms) for complex cisc
instructions. They operate as one single memory since
they all get the same address from the micro-sequencer
which handles the complex instructions. Going from 3 to
4 therefor doesn't say anything at all, it's just more
memory, or the same amount of memory with larger cells.
The rest of the architecture is visibly 3-way. The re-
order buffer, the integer schedulers, the integer ALU's.
>And what do you think about the floating point units?
>
It's virtualy identical to existing K8's. There are also 3 HT
units and not 4 as claimed by somebody at aces. It's not a K8L.
>Regards,
>
>Ten9
>
It seems to be an earlier prototype in which they were still
experimenting with the new much denser L2 cache. The fact
that they left open such a wide area with the size of the
old cache means they were not sure enough about it at that
time. Showing the cache now would imply that it must be OK.
More cache would be the most important thing for AMD to
counter Conroe's integer IPC.
Regards, Hans