AMD cuts to the core with 'Bulldozer' Opterons

Quote:

---

Originally Posted by -Boris-

The compare a module to a comparable lonely core on the same architecture. They say it's a 10% performance hit on a module design compared to true dual core.

---

So they compare scaling of their architecture? How then are two 1.8x fast modules scale up when work together ~3.6x or less :confused: If that's true marketing BS comparison is true that might be far worse than i thought i read.
Comparing scaling inside one module which is lighter than anything released since K7 see daylights of the world It's very self explanatory :D ... to AMD PR minds maybe. For others it's just confusing junk.

But that becomes practice in last 6yrs or so where performance next gen architecture (GPU i bear in mind) almost always aint compared to previous one except in first model it came out (and it's usually just top model that came out). And while cheaper iterations of new one (usually more gamer oriented) are not even compared to previous ones and across wider range on same setup. Well there's some of sits that still does reviews as they should without subjective insight but they become more of exception than a rule in overcrowded quasi-reviewer sites which serve as various PR bulletin boards (no not forums) and for incentive blogging.

You also confuse me in second sentence where again you contradict yourself with yet another "THEY" and 10% performance hit on true dual core. So they compare BD "core" to BD "module" scaling, and then again compare it to true dual core scaling and claim 10% performance degradation?

HT approach is bad for programmers. Well crafted piece of software which aligns the instructions causing no dependency stalls, cache friendly code and minimizes branches has no real benefit of HT. OTOH, a programmer who "just makes it work" without aligning the instructions nor being cache friendly and with lots of branches will see speed up by HT. However, due to all the stalls and cache misses, the HT speed up will not compensate enough, so the program ends up being slower.

There are exceptions to this though.. :)

Quote:

---

Originally Posted by hlopek

...

Yep two separate cores are always better than two threads inside one core considering power/performance ratio and better utilization and easier optimization for simpler core than to proprietary derived HyperThreading which evolved from HTT(1) inside P4-HT to HTT(2) inside Nehalem, and probably to some variation of HTT(3) in Sandy Bridge. So previous optimizations usually doesnt work and you need to recompile your work yet again and optimize for HTT beside SSE/AVX native code optimizations. But in the end SMT should serve intel as much as CMT to AMD. just CMT has brighter future regarding power wise orientation (according to AMDs bragging)

---

With such comments, you should refrain from discussing about HT ( SMT ) in the future. Basically, you're talking BS.

Quote:

---

Excellent two hits w/o miss :up: hope more of it will come, it's refreshing to see someone on forums that knows the real matter behind all HT mess mixups :clap:

---

Indeed. The head of AMD server marketing is the reference when it comes to the "real matter behind HT". :rolleyes:

please no more circular HT/SMT arguments.

Quote:

---

Originally Posted by hlopek

And above all that to mention HKMG which supposedly should serve as huge MHz jump and they even manage to squeeze 4x3.4MHz inside 90W TDP on active 45nm process

---

nope. HKMG will not improve clockspeed. it is just another necessity for energy scaling for 45nm and beyond.

in fact i would argue that HKMG is what is causing trouble for glofo 32nm SOI. the rumors about that node are not sounding very good.

Quote:

---

Originally Posted by JF-AMD

Our partners don't want to do a new microarchitecture and a new platform at the same time, so doing Magny Cours is the right move for them.

---

OFC you never what you'd mess up in your next generation (both of you guys, intel included) :ROTF: But that kind of failure could be more of catastrophe for AMD and probably wouldnt provide easy recovery solution in next gen. btw. You delayed that BD for two years ....
(* seeing yet another cpu's premature birth and architecture that came out with expectations -- Bulldozer @45nm, thru Barcelona/K10@65nm catastrophic launch as final nail in the AMD coffin?
* waiting for Sandy Bridge finalized architecture?
* waiting for finalized AVX specs?
* FMA3 to FMA4 (improvement?) changes that will better accommodate coding scheme AMD use?)
.... so it would be utterly unexpected if you came out with failure with some core that had two extra years for final development and clean out all the ghosts from it
Anyway you finally provided DDR3 support on your server platforms and also to test some of HT3.1 features that are ready (how long?) and will be part of BD and it's already there on HY-D1 chips and it's proven to work.
Is that only revision K10 that accommodate HT rev.3.1 and HTA bus? Why is there only 2x800MHz links possible when HTA is enabled?

Anyway, I also found unnecessary that turbo feature found in rev.E0 core but it's nice marketing gimmick to cope with Intels "Turbo Boost" ... far better than that silly PR ratings to cope with P4 silly frequency pushing :D. And it's certaily a good thing for people tha "need thes kind of gimmicks" ... say some 30+yrs old that have 486DX as their first computer ... they also feature that kind of Turbo gimmicks so it's all about intel's late 80s revival mode in fact :ROTF:

Quote:

---

Originally Posted by Chumbucket843

nope. HKMG will not improve clockspeed. it is just another necessity for energy scaling for 45nm and beyond.

---

yep. i know it's necessity for further lowering leakage on already low leakin SOI. And any leakage reduction should further improve clock speeds over same TDP

Quote:

---

in fact i would argue that HKMG is what is causing trouble for glofo 32nm SOI. the rumors about that node are not sounding very good.

---

That would be very bad thing. It's certainly difference between implementing same thing on bulk Si from implementing it on SOI, but GloFo claim 40% improvements implementing HKMG on 32nm over 45nm non-HKMG process and everybody said it's stunning ... but in fact it's not so stunning when we saw how 45nm HKMG process helped intel to reach almost 50% higher frequency (overclocking) than on 65nm with their Core2 tick and probably with less than equal TDP (85%-90% TDP of that OCed 65nm parts had)

Quote:

---

Originally Posted by savantu

With such comments, you should refrain from discussing about HT ( SMT ) in the future. Basically, you're talking BS.

---

They're might not be smart and destructive bs you like to wrote.

Quote:

---

Indeed. The head of AMD server marketing is the reference when it comes to the "real matter behind HT". :rolleyes:

---

It's certainly ten magnitudes better than your comment :clap: Ofc, you could try to explain to us how this HT on P4 really worked, cause it seems you have different theory.

Article from X-Bit, they quote John: AMD Bulldozer Microprocessors May Not Bring Dramatic Performance Boosts.

Quote:

---

Originally Posted by ryboto

Article from X-Bit, they quote John: AMD Bulldozer Microprocessors May Not Bring Dramatic Performance Boosts.

---

what a joke, only proves how good a review site actually is...

Quote:

---

Originally Posted by ryboto

Article from X-Bit, they quote John: AMD Bulldozer Microprocessors May Not Bring Dramatic Performance Boosts.

---

The title is too misleading. Article was translated into my native language, finally cause a lot of fear & taunt. Another little reason is so many people don't understand what the bulldozer-architecture exactly is.

the whole 50% more power for 33% more cores, thats excluding clock speeds right? so if the 32nm process is a little leaky, and to fit 16 cores in 105W it might be 100-200mhz lower than MC, and that shows how much of an IPC jump there is. (but if that is at the same clocks please ignore me)

It's not important what it is IPC wise. It is important what it is product-wise. It is claimed to be 50 % faster. It should thereby do the task 50 % faster than MC...be that with 8, 16 or heck, even 128 cores. It's 50 % regardless.

What if it was 50 % faster with 66 % more cores(considering the die-size would be the same), could the product be considered as worse than currently(33 % more cores)? If so, why?

Who honestly cares that much about single thread performance these days? Most of the real number crunching apps are already multithreaded, and more so when these chips get to the hands of us mere mortals. ...and increasingly more when BD has been in market for a while.

were only comparing 1 thing, when BD will be everywhere. knowing a little more helps speculate on what it will be like with other apps. since desktop will be limited to 8 cores, but up to 140W. if the 16 core server chip is going to be 1.1v and the 8 core desktop at 1.3v, who knows what kind of clock scaling we can see. im honestly not that concerned with servers, but thats all we have to talk about right now.

Quote:

---

Originally Posted by Calmatory

It's not important what it is IPC wise. It is important what it is product-wise. It is claimed to be 50 % faster. It should thereby do the task 50 % faster than MC...be that with 8, 16 or heck, even 128 cores. It's 50 % regardless.

What if it was 50 % faster with 66 % more cores(considering the die-size would be the same), could the product be considered as worse than currently(33 % more cores)? If so, why?

---

Correct. What matters is price\performance and for the nerds, performance per TDP and die-size.

Quote:

---

Originally Posted by hlopek

yep. i know it's necessity for further lowering leakage on already low leakin SOI. And any leakage reduction should further improve clock speeds over same TDP



That would be very bad thing. It's certainly difference between implementing same thing on bulk Si from implementing it on SOI, but GloFo claim 40% improvements implementing HKMG on 32nm over 45nm non-HKMG process and everybody said it's stunning ... but in fact it's not so stunning when we saw how 45nm HKMG process helped intel to reach almost 50% higher frequency (overclocking) than on 65nm with their Core2 tick and probably with less than equal TDP (85%-90% TDP of that OCed 65nm parts had)

---

SOI only lowers subthreshold leakage. gate leakage increases rapidly with thinner gate oxides and thin gate oxides are critical for high performance. the problem with leakage is that it is on a per transistor basis so if you double the transistors you double leakage current. on new processes you can either run transistors 10-40% faster or you can double the amount of transistors.

Quote:

---

Originally Posted by hlopek

It's certainly ten magnitudes better than your comment :clap: Ofc, you could try to explain to us how this HT on P4 really worked, cause it seems you have different theory.

---

I don't have a different theory. The people who actually implemented HT ( SMT ) have one which is different from your nonsense. But what would they know ?

Enjoy the reading ( you can start from post 52 ) :
http://www.xtremesystems.org/forums/...ght=smt&page=3

Quote:

---

Originally Posted by ryboto

Article from X-Bit, they quote John: AMD Bulldozer Microprocessors May Not Bring Dramatic Performance Boosts.

---

They quote me but I think that I haven't spoken to Anton in more than a year, and probably only discussed magny cours. That should give you enough background.

Quote:

---

Originally Posted by JF-AMD

They quote me but I think that I haven't spoken to Anton in more than a year, and probably only discussed magny cours. That should give you enough background.

---

I didn't hear anybody complaining when your competitor achieved 33% more
performance with 50% more cores in Westmere.... :)


Regards, Hans

Hans, the next time I am in the Netherlands I owe you a beer. Thanks for that one!

Quote:

---

Originally Posted by Calmatory

It's not important what it is IPC wise. It is important what it is product-wise. It is claimed to be 50 % faster. It should thereby do the task 50 % faster than MC...be that with 8, 16 or heck, even 128 cores. It's 50 % regardless.

What if it was 50 % faster with 66 % more cores(considering the die-size would be the same), could the product be considered as worse than currently(33 % more cores)? If so, why?

Who honestly cares that much about single thread performance these days? Most of the real number crunching apps are already multithreaded, and more so when these chips get to the hands of us mere mortals. ...and increasingly more when BD has been in market for a while.

---

I have the same viewpoint for GPUs. Unfortunately, Nvidia / Intel's favourite argument against 'more cores' is to press for core to core comparisons, which are logically invalid as you don't buy cores, you buy a product.

I don't see anything wrong if a CPU with more cores delivers 50% more performance consistently over varied workloads. So long as it is priced competitively vis a vis its performance, I'm completely fine with that.

Quote:

---

Originally Posted by duploxxx

what a joke, only proves how good a review site actually is...

---

Exactly. (But i disagree they're in fact good reviewer site when you get them real product) and this is a reiterated news post (and A.Shilov is only news guy that doesnt care about all that too much:D)

That xbitlabs article AMD Bulldozer Microprocessors May Not Bring Dramatic Performance Boosts is a joke. Anyone reading some forum could wrote it more correctly and with some level of interest ... ex. "the first Bulldozer micro-architecture desktop/workstation chip code-named Zambezi (which belongs to Orochi family, according to the firm) will feature eight x86 processing engines with a multithreading technology, two 128-bit FMAC floating point units, shared L2 cache, shared L3 cache as well as integrated memory controller. AMD also states that the new CPU will feature “extensive new power management innovations”."

So he refers to Nov2009 slides and he didnt yet figure out that FMACs are two per module and not "two per core (x8)" or shared L2 cache will be shared a) between eight cores or b) between core and what. And as usual xbitlabs wrote (pump) that news at least 3rd-4th time since originally one on their site cover that matter (only if someone wish to count), and delivering nothing new or explanatory. As it seems xbitlabs also don't like to talk about unreleased products also.

Quote:

---

Originally Posted by Hans de Vries

I didn't hear anybody complaining when your competitor achieved 33% more
performance with 50% more cores in Westmere.... :)


Regards, Hans

---

The difference is that Westmere is really fast, almost ridiculous IPC. MC is fast to, but it's IPC/core really needs some improvement for desktop users.

It doesn't matter much if Zambezi will be quicker than Phenom II if the performance gap between AMD and Intel continue to grow.

Quote:

---

Originally Posted by -Boris-

The difference is that Westmere is really fast, almost ridiculous IPC. MC is fast to, but it's IPC/core really needs some improvement for desktop users.

It doesn't matter much if Zambezi will be quicker than Phenom II if the performance gap between AMD and Intel continue to grow.

---

What CPUs are in practice better than x6 1090T? Hm...i7 965 is simillary, and better is only i7 975 + i7 980X (970). Firstly i read maybe all reviews from world (its my hobby), so sorry, but your arguments are irrelevant for me in this.

SB will not faster than Gulftown, only in memory benchmarks:rofl:. Next highend of SB will at 3Q 2011, mainstream SB will atacking segment about i5 750 - i7 950.

Quote:

---

Originally Posted by FlanK3r

What CPUs are in practice better than x6 1090T? Hm...i7 965 is simillary, and better is only i7 975 + i7 980X (970). Firstly i read maybe all reviews from world (its my hobby), so sorry, but your arguments are irrelevant for me in this.

SB will not faster than Gulftown, only in memory benchmarks:rofl:. Next highend of SB will at 3Q 2011, mainstream SB will atacking segment about i5 750 - i7 950.

---

In practice?
It's in practice Phenom II X6 needs to be faster. In practice IPC is more important than cores, since desktop-programs don't scale that well. I'd say that for the average user Core i5 750 would be a better choice. Besides, you can overclock it 50% with ease, sometimes a good bit higher than that, you can't do that with a Phenom II.

http://www.xbitlabs.com/articles/cpu...t_6.html#sect0

http://www.anandtech.com/show/3674/a...55t-reviewed/9

1090T is a good choice for bulldozer, you don't need buy a new motherboard next.

So it's cheaper and as fast, even faster. it's in line with i7 965 already, and can clock too like hell.

Quote:

---

Originally Posted by madcho

1090T is a good choice for bulldozer, you don't need buy a new motherboard next.

So it's cheaper and as fast, even faster. it's in line with i7 965 already, and can clock too like hell.

---

You should back that up with some benchmarks. Benchmarks in programs that users need performance in most frequently.

Quote:

---

Originally Posted by Hans de Vries

I didn't hear anybody complaining when your competitor achieved 33% more
performance with 50% more cores in Westmere.... :)


Regards, Hans

---

touche... i guess they must be on that intel kool-aid

Quote:

---

Originally Posted by -Boris-

The difference is that Westmere is really fast, almost ridiculous IPC. MC is fast to, but it's IPC/core really needs some improvement for desktop users.

It doesn't matter much if Zambezi will be quicker than Phenom II if the performance gap between AMD and Intel continue to grow.

---

superpi is your day to day task that you enjoy with the gf and the familly???


i bet you enjoy your collection of blu ray movies more right??? rip them and encode them ...this will require more cores ... wich amd is pretty close to intel in $/performance ..... but yeahh i get your point... single thread performance counts more then core count