AMD cuts to the core with 'Bulldozer' Opterons

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02-24-2010, 10:00 AM
kl0012

Quote:

Originally Posted by informal

Why isn't it a good thing? You won't see sky-high sisoft sadra mem benchmark ? On desktop 3 or more channels are useless even for an 8 core chip as Orochi. 2 channels of DDR3 @ 1600Mhz (jedec standard) is perfect.

This is not exactly true.
http://ixbtlabs.com/articles3/cpu/ar...2009-7-p1.html
Up to 18% gain in some desktop apps from the third mem channel. For more cores and higher frequency the gain may be much larger. Now if you consider real multitasking (running many apps in parallel) the diff can be even higher. This is why 6-core opteron dosn't show perfect scalability in SpecINT/SpecFP.

Quote:

Why do you need higher HT link speed ??

16GB/s current agregate HT BW is equal to BW of one PCIe x16 slot. Considering upcoming SATA3, USB3, PCIe3 (and all this with CF config) this probably going to be a bottleneck.
02-24-2010, 10:20 AM
informal

Up to 18% you say? You can get the 20% if you use 1600Mhz jedec ddr3 dual channel memory instead of 1333Mhz one. There goes you 3rd channel advantage away without additional routing on the pcb level of the board and zero cost to the CPU die area... BTW, 6 core Opteron is using regged DDR2 800 memory,not regular DDR3 1600Mhz one BD will use.

The HT link won't be the bottleneck I assure you....
02-24-2010, 11:24 AM
crazydiamond

lol just when you think you heard it all, now giving end users a good upgrade path is a bad thing :lol: maybe every single cpu should have its own socket :rofl:

also, informal, you must have a lot of patience :)
02-24-2010, 11:50 AM
kl0012

Quote:

Originally Posted by informal

You can get the 20% if you use 1600Mhz jedec ddr3 dual channel memory instead of 1333Mhz one.

Yeh, right...

Quote:

The HT link won't be the bottleneck I assure you....

Yeh, very convincing arguments...

Quote:

Originally Posted by crazydiamond

lol just when you think you heard it all, now giving end users a good upgrade path is a bad thing maybe every single cpu should have its own socket

I wonder if anyone of those who defend "upgrade path" even uses some old AM2 board with latest phenom2. What I see is the impatience in waiting for upcoming 890FX chipset to exchange their "outdated" 790FX just because of the presence SATA3. :welcome:
02-24-2010, 11:56 AM
Chumbucket843

Quote:

Originally Posted by informal

Up to 18% you say? You can get the 20% if you use 1600Mhz jedec ddr3 dual channel memory instead of 1333Mhz one. There goes you 3rd channel advantage away without additional routing on the pcb level of the board and zero cost to the CPU die area... BTW, 6 core Opteron is using regged DDR2 800 memory,not regular DDR3 1600Mhz one BD will use.

The HT link won't be the bottleneck I assure you....

soft errors scale exponentially with frequency, not a good idea for large machines. in hpc the third channel plus hyperthreading make nehalem much faster than previous cpu's, its all about spmv.
02-24-2010, 12:15 PM
informal

Quote:

Originally Posted by kl0012

Yeh, right...

Yeah,it's called math, 1600/1333. And it's called economics (3 channel routing on a board is pita compared to 2 channel;cost is higher for the 3 ch. IMC compared to 2 channel one-pure logic). We are talking about client space here.IN server/workstation space AMD will offer 2/4 channels and 2/4x times teh core count.

Quote:

Yeh, very convincing arguments...

In client space HT3.0 is an overkill,show me the opposite in any review. IMC is decoupled from this clock so it makes no difference to clock it any higher. Platform is not I/O bound in any case or any review.

Quote:

I wonder if anyone of those who defend "upgrade path" even uses some old AM2 board with latest phenom2. What I see is the impatience in waiting for upcoming 890FX chipset to exchange their "outdated" 790FX just because of the presence SATA3.

AM3 will not be an "old" platform,all current AM3 boards support anything end user may need.The latest 890 ones support sata6 and latest usb standard(it's not a must-have as you want to portray it though,I'm fine with my AM2r2 board,OCs great and performs just as well).
02-24-2010, 12:32 PM
N19h7m4r3

Quote:

Originally Posted by kl0012

I wonder if anyone of those who defend "upgrade path" even uses some old AM2 board with latest phenom2. What I see is the impatience in waiting for upcoming 890FX chipset to exchange their "outdated" 790FX just because of the presence SATA3. :welcome:

Running an Abit KN8 Ultra with a Phenom CPU.

No need to change it yet as it does it's job well.

I'll Upgrade it to AM3 or what ever is out at the time, I need to. Not before, as I have no need for SATA3 yet.
02-24-2010, 12:55 PM
generics_user

Quote:

Originally Posted by kl0012

This is not exactly true.
http://ixbtlabs.com/articles3/cpu/ar...2009-7-p1.html
Up to 18% gain in some desktop apps from the third mem channel. For more cores and higher frequency the gain may be much larger. Now if you consider real multitasking (running many apps in parallel) the diff can be even higher. This is why 6-core opteron dosn't show perfect scalability in SpecINT/SpecFP.

16GB/s current agregate HT BW is equal to BW of one PCIe x16 slot. Considering upcoming SATA3, USB3, PCIe3 (and all this with CF config) this probably going to be a bottleneck.

HT BW is supposed to be pushed above 20gb/s with bulldozer

and if you take a look at desktop performance you will notice that you see no gain AT ALL by overclocking the HT bus which clearly indicates that it isn't a bottleneck at all
02-24-2010, 01:33 PM
Macadamia

Quote:

Originally Posted by Chumbucket843

soft errors scale exponentially with frequency, not a good idea for large machines. in hpc the third channel plus hyperthreading make nehalem much faster than previous cpu's, its all about spmv.

On server Bulldozer/Magny G34 will have four mem channels. Where does the argument stand now then?
02-24-2010, 01:37 PM
Oliverda

Quote:

Originally Posted by N19h7m4r3

Running an Abit KN8 Ultra with a Phenom CPU.

No need to change it yet as it does it's job well.

I'll Upgrade it to AM3 or what ever is out at the time, I need to. Not before, as I have no need for SATA3 yet.

With beta or mod BIOS?:eek:
02-24-2010, 01:44 PM
Chumbucket843

Quote:

Originally Posted by Macadamia

On server Bulldozer/Magny G34 will have four mem channels. Where does the argument stand now then?

the argument is the same as of now because bulldozer does not exist yet. if AMD has 4 memory channels in the future then it will be a great hpc platform. idk if intel has plans for 4 channels.
02-24-2010, 01:50 PM
madcho

Quote:

Originally Posted by Macadamia

On server Bulldozer/Magny G34 will have four mem channels. Where does the argument stand now then?

memory bandwith is very good for servers. It's nice with databases.
02-24-2010, 01:55 PM
informal

Quote:

Originally Posted by Chumbucket843

the argument is the same as of now because bulldozer does not exist yet. if AMD has 4 memory channels in the future then it will be a great hpc platform. idk if intel has plans for 4 channels.

4 memory channels and DDR3 support come with 8/12 core Magny Cours chips this quarter ;). MC and Bulldozer share the same server platform,so BD cores ,the 16 core parts for G34 socket,will support it too.
02-24-2010, 02:57 PM
N19h7m4r3

Quote:

Originally Posted by Oliverda

With beta or mod BIOS?:eek:

Friend of mine said he got a beta bios. I have no idea where the bugger got it, but since I gave him the board he's in heaven.

Although it's only a Phenom 9600 in it though.

I'm currently hunting to see if there's a way to get a Phenom 2 or Athlon 2 in there.

On a side note, my M2N-Sli Deluxe also has a Phenom 2 920 in it.

I don't get why some people seem to think that just because it's not a native Am2+ or am3 board its useless.

These old boys have some life left in them
02-24-2010, 04:59 PM
RaV[666]

Quote:

I wonder if anyone of those who defend "upgrade path" even uses some old AM2 board with latest phenom2. What I see is the impatience in waiting for upcoming 890FX chipset to exchange their "outdated" 790FX just because of the presence SATA3.

Well, im using foxconn A79A-S ,for over a year now, with phenom 2.In few months its gonna be upgraded with Phenom X6,for a year more of usage.Thats bad ?
And most of my friends machines are running Am2 or Am2+ mobos with current cpus.Even if bios officialy doesnt support a cpu ,most of the time it works just fine.
My next mobo will be Am3r2 with a bulldozer, but thats more than a year away for me, so yea.Platform longevity is important to a lot of people.
02-24-2010, 05:30 PM
haylui

Quote:

Originally Posted by kl0012

Yeh, right...

Yeh, very convincing arguments...

I wonder if anyone of those who defend "upgrade path" even uses some old AM2 board with latest phenom2. What I see is the impatience in waiting for upcoming 890FX chipset to exchange their "outdated" 790FX just because of the presence SATA3. :welcome:

ya...you're right
AMD, shouldn't let current AM3 users have any chance to upgrade from Phenom II/Athlon II they are using; Just same like Intel did to their LGA1156, lolz...
For me, as an end user/desktop user, I don't benefit at all from increase HT speed/BW; So why don't let BD be totally compatible with current AM3 boards? It would help the sales when BD is launched and keep existing users happy. Win-Win situation, why not?

.
02-24-2010, 05:31 PM
haylui

Quote:

Originally Posted by crazydiamond

lol just when you think you heard it all, now giving end users a good upgrade path is a bad thing :lol: maybe every single cpu should have its own socket :rofl:

also, informal, you must have a lot of patience :)

that guy is just don't understand the whole picture
all he see is more memory channels, i7? and higher HT speed
lolz
02-24-2010, 10:13 PM
kl0012

Quote:

Originally Posted by informal

Yeah,it's called math, 1600/1333. And it's called economics (3 channel routing on a board is pita compared to 2 channel;cost is higher for the 3 ch. IMC compared to 2 channel one-pure logic). We are talking about client space here.IN server/workstation space AMD will offer 2/4 channels and 2/4x times teh core count.

Initial bulldozer targets high-perf desktop segment were the compability is much less important then performance. Computer entusiasts usually tends to buy latest and fastest hardware. Other 95% of users will never open the cover of system box. Mainstream users will still get a new socket with upcoming integrated processor.

Quote:

In client space HT3.0 is an overkill,show me the opposite in any review. IMC is decoupled from this clock so it makes no difference to clock it any higher. Platform is not I/O bound in any case or any review.

And how do you calculate influence of upcoming features (SATA3, USB3, PCIe 3.0) on system performance with current 4000Mt/s HT link?

Quote:

AM3 will not be an "old" platform,all current AM3 boards support anything end user may need.The latest 890 ones support sata6 and latest usb standard(it's not a must-have as you want to portray it though,I'm fine with my AM2r2 board,OCs great and performs just as well).

Good for you. But please dont decide for all users what they will need in 1.5 year from now.

What impress me most is the fact that people who used to blame Intel for lack of inovations and using FSB in desktop, now suggest AMD to do almost same thing just for ghostly "compatability" while a good new MBs cost less then $100 already. "Users don't need more mem channels...", "users don't need faster HT..." remainds me something.
02-25-2010, 12:06 AM
mindfury

Quote:

Originally Posted by kl0012

And how do you calculate influence of upcoming features (SATA3, USB3, PCIe 3.0) on system performance with current 4000Mt/s HT link?

SATA3 and USB3 is bottlenecked by southbridge,more HT link bandwidth will not help.

PCIE3.0 will not show up before 2012.
02-25-2010, 01:00 AM
Oliverda

Quote:

Originally Posted by N19h7m4r3

Friend of mine said he got a beta bios. I have no idea where the bugger got it, but since I gave him the board he's in heaven.

Although it's only a Phenom 9600 in it though.

I'm currently hunting to see if there's a way to get a Phenom 2 or Athlon 2 in there.

On a side note, my M2N-Sli Deluxe also has a Phenom 2 920 in it.

I don't get why some people seem to think that just because it's not a native Am2+ or am3 board its useless.

These old boys have some life left in them

Sounds good.:) Can you send me that beta BIOS?
02-25-2010, 01:02 AM
N19h7m4r3

Quote:

Originally Posted by Oliverda

Sounds good.:) Can you send me that beta BIOS?

I'll see if the man still has it, haven't been to his in ages.

I'll PM you later today with it :D

#Edit, oh bugger, I ment KN9 Ultra BTW, not KN8 very very bad typo :(
02-25-2010, 03:41 AM
FlanK3r

Quote:

Originally Posted by kl0012

Initial bulldozer targets high-perf desktop segment were the compability is much less important then performance. Computer entusiasts usually tends to buy latest and fastest hardware. Other 95% of users will never open the cover of system box. Mainstream users will still get a new socket with upcoming integrated processor.

:up:right! Bulldozer will at 2011 for entusiasts and lower CPUs as LIano and Thubans for normal segment. Yes, im a bit entusiasts, i need Bulldozer, i need Thuban next 2 months etc etc.
Srry for 90% guys, but AM2/AM2+ is death platform for future. History s.AM2 is about s939, this was very simillary socket with only DDR1 and how long years ago? :-/
08-04-2010, 04:26 AM
hlopek

Quote:

Originally Posted by Smartidiot89

No.

It doesn't meen 2 Bulldozer "cores" will be only 80% faster than 1 K10.5 core they aren't even comparing K10.5... 1 Bulldozer Module will be faster than 2 K10.5 cores by good margins.

Right, you really dont understand what you read. They compare that Bulldozer module to a current K10/K10.5 class core which has 128-bit FP SSE and 2x 64-bit port INT SSE, and claim to be as much as 1.8x faster than current single core. So that raw math and virtual 90% performance of K10 single core is basically ok.

They "sacrifice performance" cause in most cases third pipeline/port causes more heat than benefits. That's rather known fact since P6/K7 times where there was studies how would adding more than three ALU+FP inside core impact performance and heat output, and they saw only opportunity to go no multicore design which are now widespread and common. Now they light up cores cause they oriented software world towards efficient threaded software designs, and there's nothing too bad to it except we don't see anymore enormous serial processing speed bumps as we did until Y2K.
08-04-2010, 05:26 AM
-Boris-

Quote:

Originally Posted by hlopek

Right, you really dont understand what you read. They compare that Bulldozer module to a current K10/K10.5 class core which has 128-bit FP SSE and 2x 64-bit port INT SSE, and claim to be as much as 1.8x faster than current single core. So that raw math and virtual 90% performance of K10 single core is basically ok.

You should read the article again.
The compare a module to a comparable lonely core on the same architecture. They say it's a 10% performance hit on a module design compared to true dual core.

Everywhere they state that HT has ~25% performance boost while a module has a 80% performance boost.

So, a bulldozer module is 1.8x as fast as a singlecore.

Read this sentence again:

Quote:

As it turns out, this sharing of components across the cores impacts performance. Fruehe says that a pair of Bulldozer "cores" will yield about 1.8 times the performance of what a single, whole core would have."

And read this quote from informal where he quotes chuck moore at AMD.

Quote:

Bulldozer module can achieve ~80% speedup when running 2 threads (versus ~25% from hyperthreading)
08-04-2010, 09:06 AM
hlopek

Quote:

Originally Posted by madcho

i seriously hope that amd will deliver same amount of BD modules than intel cores. But i'm think this is not possible.

Why ? Because BD cores a lot bigger than older cores, even 32nm will not be enough for that, but BD modules are better than 1 intel cores with HyperThreading, that's easy too understand without any doubt.

On K10.5 6MB L3 cache consumes almost same space as four cores with their proprietary 512kB L2 cache

Bulldozer cores will be lighter (maybe smaller L1 cache per "core" that will total up to same size of 64+64kB inside dual core module as in K7-K10.5 releases And L2 will be same or 1024kB per module so they could easily squeeze up to 6 that kind of modules and again double L3 cache to 12MB (originally they mentioned that 16MB L3 is projected for Bulldozer CPU afair) and still be inside same dimensions as previous CPU generations, K10@65nm/K10.5@45nm ~250mm2. And above all that to mention HKMG which supposedly should serve as huge MHz jump and they even manage to squeeze 4x3.4MHz inside 90W TDP on active 45nm process

Yep two separate cores are always better than two threads inside one core considering power/performance ratio and better utilization and easier optimization for simpler core than to proprietary derived HyperThreading which evolved from HTT(1) inside P4-HT to HTT(2) inside Nehalem, and probably to some variation of HTT(3) in Sandy Bridge. So previous optimizations usually doesnt work and you need to recompile your work yet again and optimize for HTT beside SSE/AVX native code optimizations. But in the end SMT should serve intel as much as CMT to AMD. just CMT has brighter future regarding power wise orientation (according to AMDs bragging)

Quote:

Originally Posted by madcho

AMD's way is beautyfull, a real bruteforce in integer; the big lack in K8, and the big problem of the K10 as my mind. And my best hope, that is AMD will enable with SSE5 to use FPUs of the GPU for CPU calcs. That's maybe why the FPU on BD is lower than on K10 ( lower with the same amounth of threads ) same if you concider that a BD is a new core.

SSE5 is part of CPU "module" and until GPU part of CPU doesnt get inside "module" it wouldn't serve as GPU optimization and that will probably never happen. Integrated GPU (which is not part of Bulldozer btw) will communicate over PCIe (and i hoped for HT/HTX bus) and that way will only serve for better integration and better HTPC (low end server design?). Only performance boost that "SSE5" could done would be some packing that shrink bandwidth needed for PCIe communication or something but that would benefit to any device connected to that PCIe(3.0?) bus (ex. discrete GPU card) and dont think they even think about that kind of tweaks when they designed SSE5.

Quote:

Originally Posted by Helmore

One limiting factor in core scaling though, is that AMD has apparently designed its cache structure in such a manner to only allow 4 modules to share their L3 cache. For AMD this means they will have 2 separate L3 cache pools when they put 8 modules on a single die and I don't think we will be seeing 8 BD modules single die CPUs for their first generation BD chips. I could be wrong though on this one, have to read up on it again.

And what about 6-core revisions of K10(.5) CPUs, couldn't every core use ondie L3 cache and it's still 48-bit wide as in quad-core (Deneb, PII X4)?

I think L3 sharing is pretty easy to upgrade to more than 4-cores when TLB works properly in the first place (famous pre-B3 K10 revisions).

Quote:

Originally Posted by JF-AMD

HT originally came about in P4 because they had a very long pipeline and one cache miss had lots of penalty associated. But as they shortened the pipeline (i.e. Core2) they tossed out HT because they no longer needed that band-aid.

Excellent two hits w/o miss :up: hope more of it will come, it's refreshing to see someone on forums that knows the real matter behind all HT mess mixups :clap:

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