Originally Posted by matt9669
For the confused: the "Venice" cores are the Revision E (or E4 stepping) 512KB L2 Socket939 Athlon 64 chips. They are produced on a 90nm strained silicon-on-Insulator process and are SSE3 enabled. IPC simply describes a chip's performance on a per-clock basis - if chip A is faster than chip B at 2GHz, chip A has higher IPC, regardless of how or why. A die shrink does not inherently increase the per-clock output of any semiconducting device, die shrinks increase "performance" in the way of better yields (for a given frequency) and higher frequencies (for a given yield), manufacturers sometimes refer to performance in this way.