never looked at there scores........... dont care.
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never looked at there scores........... dont care.
You don't understand. Because he has chips (IF he has, of course), he still feeds with results slowly. For example he posts screenshots with all fields hidden and then releases new ones opening one field by one every next week.Quote:
Originally Posted by Andi64
I don't care much if they good or not, but I'm sure real results will be significantly different, better or worse.
So, who'd need such a bs...
If I had a nickel..... :DQuote:
Originally Posted by RaV[666]
here is my honest opinion the reason why everyone is think bulldozer is fail is because amd said they where out to target Nahelam and nothing more.
it's not like they didn't see sandybridge coming it's was plastered all over the internet how much faster it was going to be then Nahelam. even before they had a bulldozer that module concept.
Exactly why I feel Bulldozer will essentially match Nelahem CPC. If we can get 5 Ghz over 8 cores at that single thread speed at a reasonable price, people will love Bulldozer. To be honest, Core i7 was so much faster than Phenom II there was no point in buying Phenom II, especially after X6's were costing the same as a 920/860. We are basically running Core 2 equiv machines with these CPUs (+2 cores) now...in the beginning, PII couldnt even match Core 2. Luckily CPUNB overclocking helps that a bit.Quote:
Originally Posted by demonkevy666
The ~15% CPC difference between Nelahem and Sandy Bridge though, thats quite substantial. I'd see a bulldozer chip at 5 Ghz equaling sandy bridge at about 4.2-4.4 at best
http://www.ackuna.com/badtranslator
Write in Advanced Micro Devices.
Pick 56 translations.
:banana::banana::banana::banana: bricks
Quote:
Originally Posted by andos
If you enter "Intel Corporation" and 56 translations the result is:
"Intellegence"
It's a conspiracy I tell ya!!! :rofl:
Way OT, I know, just couldn't resist...
Dave, That is why Intel is called "Intel". It wasn't by accident, they just assumed they'd be inteligent:p:
I was just watching this clip about Deus Ex: Human Revolution:
http://www.youtube.com/watch?v=teldc...ailpage#t=322s
and Peter Ross mentions that they are excited because they "have the opportunity to include the game free with purchase of some select AMD hardware coming very soon" he also mentions that he can't talk about those just yet. Now I was wondering, is there any chance that they might include the game with the FX processors? He is after all talking about something "coming very soon" and I'm not aware of any Radeon-cards being released any soon. Also, the Radeon-cards are already shipping with DiRT 3 copies aren't they?
Now this is probably a long shot but I found it rather interesting, anyone have any idea where we might see this game being included? :)
When is that game launching? There will be new radeaons end of this year they say.
I also noticed Dirt 3 was also with the new APU's
Got a pic on the box and no code :(Quote:
Originally Posted by charged3800z24
AMD cards are coming very soon, also, the guy he is speaking too replies with "does that mean I can get a card too then". Kinda implies they are discussing vliw4g2 and GCN hardware.Quote:
Originally Posted by Warwian
AMD are running hard samples of both from what will become retail steppings.
Price was the reason i bought my first AMD system and it did the job i needed it to do.
If the Bulldozer is a little slower than the Sandy-Vag but cheaper ill stick with AMD.
Hahah good one. Same here, I've ended up staying with AMD due to platform costs.Quote:
Originally Posted by Baam
I end up stay with AMD after I didn't manage to get AMD K6-2...Quote:
Originally Posted by sr4470
http://semiaccurate.com/2011/08/04/b...n-really-soon/
ps from the comments: 1802617757855.0835 furlongs / speed of light = 14.000002 days
and where did charlie get that number from
After all this waiting BD better perform a lot more than people ever expected. the 60-90 days have spanned to almost 120 days, and who knows how long it will take to see it in stock around here!
perform a lot better than expected? imagine huge disappointment if it doesnt perform enough because it is too late? not logical.. :p I think one gets more perf per cpu (more cores).. we'll see!
what I want to see is huge OC capability. maybe not from first stepping, maybe second or third then I want get 5ghz stable :D
wait.. wait.. but im happy with 955 for general use though and OCing new stuffs is fun hobby
Don't get me Wrong I already have a CHVF And I'm waiting for BD to be launched Luckily I will be going on my early leave from work this month for 36 days and when i get back i won't have enough money to spend on a CPU until early November I think :p: I also hope it OC a lot better than my 1090t and runs cooler on AIR or in My case the H80.
http://4.bp.blogspot.com/-139hqHAz9Y...TA/s1600/6.png
Assuming he has a retail stepping, can anyone possibly explain why the FPS are so low on the 8150? They're barely beating the X6 1100T. Seems like something is really wrong with this bench.
who is that? is there a link to the article or other images?Quote:
Originally Posted by freeloader
That's the famous banned on XS person we shouldn't even link to his blog here. [OBR if you're confused]Quote:
Originally Posted by muziqaz
There are more pics but don't bother looking, because they might be fake.
Man, why people even bother posting anything from him? He admitted faking BD tests a while ago.Quote:
Originally Posted by Lightman
And to answer freeloader's question: FPS are so low because they are from OBR imagination.
it is hard enough to imagine that Phenom II x6 would be twice as slow than 6 core i7 :D
OBR is a piece of :banana::banana::banana::banana:. 100% fake and has too much spare-time of making all bs crap images... He has NOT a bulldozer sample, and has never had. Wait for the cpu and don't waste so much energy on speculating.
Best regards from Sweden!
Giving OBR attention is like feeding a troll, they will just continue. Every time someone talks about OBR Bulldozer IPC goes down so please stop it:D
Man, every post that mentioned about THAT IDIOT had been deleted by admin in this forum. Don't waste your mind and resources to discuss anything about him.:)
EDIT:
Seems some guys emulate FX-6110 by using ES FX-8130p and compared to 2600k and 1100T. I don't have time to observe every result, and don't know whether it could reflect any problem.
http://www.f-paper.com/?i708835-Phot...lation-testing
september / october
I've read the article. It doesn't look so good for Bulldozer single thread performance. I hope for AMD's sake that they've concentrated more on IPC then simply adding more cores. I guess we will know in about five to six weeks. :)
Did I understand it correctly? They took Phenom II x6 overclocked it, gave it 1866Mhz ram and called it a FX-6110? Man that's even worse than OBR :(Quote:
Originally Posted by undone
It's like simulating core 2 duo using pentium 4 :/
BD module may have 20% better IPC than K10.5 core, because of better memory reordering, faster cache hierarchy, wider front end, beefer branch prediction, bigger L2 cache, and faster memory controller and L3 cache. Also, BD module can execute 2 ALU, 2 AGU, 2 intSSE and 2 fpSSE operations per cycle per thread. BD module is 4-issue design versus 3-issue K10.5. L1D cache is write trough and smaller than K10, but WT performance penality is compensated with WCC - Write Coalesce Cache. L1D is also 4 times smaller than K10.5, but it is 4-way associative, and 16K 4-way WT cache may have 92% hit rate, 64K 2-way L1D has a little better hit rate, something about 94%. But that isn't problem, because branch predictor is better, L2 is bigger and has better hit rate. 4-cycle use to load latency is hidden by 2-4 stage longer pipeline.
BD pipeline is optimised for 15-20% higher frequency than K10 pipeline at same process node. Because of that, with turbo core 2, BD single thread performance may be much better than K10.5, and something on pair with Sandy Bridge.
Multithread performance isn't that much better. It may be 35-45% better than six core thuban, and maybe little bit lower than 6-core SB-e and Westmere.
FX8 has 8 small cores but SB-e has six fat, hyperthreaded cores, with at least 30-35% better IPC. However, FX8 with 4 modules may have low TDP and high frequency, much higher than six core i7.
My assumption is that the 4 module BD have 10% better multithread performance with same thermal than 4-core SB, if we count on Amdahal's law, turbo core 2, memory bandwidth and latency and shared module resources. Single thread performance may be on pair with SB, with same thermal envelope.
In comparision with Westmere, 4 module BD have 10-15% lower multithread performance. Maybe 10-core Komodo should outpace six core Westmere, and be on pair with SB-E.
Here is my little study about prediction of BD performance. :)
LOL! :DQuote:
Originally Posted by muziqaz
My predictions is based on math. Light multithreaded software has lower paralelisation, arround 0.7, and heavy multithreaded code has 0.95 paralelisation. FP intensive code also contain lot of integer code. Cinebench for example has 0.6 IPC for integer and 0.7 IPC for FP on K10 core. FPU is underutilised, because max for FP is 2 packed FP-SSE operations or 2x integer SSE and shuffle on K10 core. With BD module max. is 2 packed FP SSE or FMA + 2 integer SSE or FMA or 1 int SSE + 1 shuffle.
Easily seen, FP core is underutilised with IPC=0.7. With 2 int threads FP IPC for both threads can go up to 2, but hardly more.
Per thread FP IPC can be 0.8, and int IPC can be 0.7. That is 15-20% better per core IPC than K10. With 33% more cores, 15% better average IPC, and 15% higher frequency, overall multithread performance in FP intensive applications can be up to 55-60% better than Thuban. Also if IPC per core is same or little lower, because of shared resources, with higher frequency and more cores in such FP intensive applications performance can rise up to 40%, which is good.
10% better in multithreading than SB 4c/8t sounds too low.
you state that single thread perf will be much higher than thuban, but keep in mind that if its 10% faster clocks, 10% higher IPC (after the loss due to 2 cores in one module), and 33% more cores than thuban, it should be 60% faster than thuban in multithreading (think cb11.5)
if you believe that 1 core vs 1 core of BD vs SB will be pretty close to each other, then why do you think 8 cores will struggle against 8 threads?
They did more to BD then just increase clock speed. And i didn't see that they did with the turbo for the x6? Did they have it off?
Depends of type of workload. If module utilisation is high, difference will be lower. 8-core BD has only 4 FPU units.Quote:
Originally Posted by Manicdan
Compare to Thuban, IPC per module could be 20% higher, but IPC per module may be equal, or little bit higher, something arround 10%. Threads doesn't scale linear to core count, because of Amdahal's law.
For 33% more cores due to Amdahal's law, and CB paralelisation of 95%, with same IPC cores you can squezee only 23.5% more performance. With core and thread count performance convergent to constant value.
For 20% IPC improvement for BD module vs K10 core, there could be 8-9% improvement for BD core IPC if we know that the BD core IPC = 0.9 BD module IPC per thread .
Calculation for CB is 1.09(IPC)x1.1(frequency)x1.23(core scaling) = 1.47x Thuban 1100T. With lower paralelisation or higher module utilisation, difference could be lower, close to 35%.
X6 at 3.8 and FX-8130P at 6 cores 3.8.Quote:
Originally Posted by muziqaz
BD has 8x 128bit FPUs, OR 4x 256bit FPUs
funny how you come to 1.47x when you already factored in the inefficiencies, then drop it down to 35% just because?
So why not include 8130's performance at 3.8ghz?Quote:
Originally Posted by BeepBeep2
BD FPU can issue up to four instructions, but front end can issue maximum 4 instructions + branch fusion. With two threads, with high ILP, BD core can retire up to 2 instructions per cycle which in realiti can't go over 1.6-1.8. For example, Phenom II core can reach 2.4 IPC with Linpack of max. 3 IPC. BD module probably can reach up to 3.5-3.6 IPC with two threads, which is 1.7-1.8 IPC per thread. With such heavy workload, BD core can issue less instructions than K10.5 core. But, there is rather exception than rule. In that case 8 core BD or 4 modules in BD can retire up to 14.4 instructions per cycle. Phenom II X6 can retire same 14.4 IPC with six cores.
For example: CB10, has 1.3 IPC on K10 core, but CB10 can reach 1.5 IPC with SB core. This is 50% faster than Phenom II X6 in such workload with 33% more cores.
I was correct my calculations. There was a error. ;) ~30% is in case of high ILP code, with IPC up to 2 per thread or ~50% difference with lower ILP.Quote:
Originally Posted by Manicdan
Attachment 118752
I've done simulation sheet for six core 3.2 GHz 6120p 95W BD. It is 0-35% faster than Thuban 1100T. Ipc is little higher because of lower frequency. IPC doesn't scale linear with frequency increase.
Attachment 118753
Agreen on mentioning "unmentionable" )Quote:
Originally Posted by undone
but that link is not better:
Attachment 118755
I made a small comparison between Core duo, SB, K8, K10 and BD.
https://public.sheet.zoho.com/publis...v-architekture
If something is wrong just comment and I will correct the mistakes.
You may want to add L1, L2 and L3 cache speed to that chart. Nice graph.Quote:
Originally Posted by TESKATLIPOKA
I don't know their cache speeds, just the latency.
L1 load to use latency is 4 cycles. Branch mispredict latency is 16-cycles, which implies that integer pipeline is 16-stages long. Also some simple ALU operations has 2 cycles longer latency. BD pipeline must be 14-16 stages for integer and 19-21 cycles for FP. ;)
BD module has 2x 2ALU + 2AGLU.
BD L1D can do 1x256 bit load (AVX), and 1x128-bit store at the same time, or 2x128-bit load and no one store, because BD core is limited to two memory operations because of 2 AGU.
Other combinations are 2x128-bit load, 1x128-bit load and 1x128-bit store, 2x64-bit store.
Like SB, BD L1D has data cache bandwidth of 384 bit/cycle in both directions.
K10 L1D can do 2x128-bit load, 1x128-bit load + 1x64-bit store, 2x64-bit store effectively 256-bits/cycle.
I will add the value 14-16 for pipeline at least until we won't know the real number.
2x64-bit store effectively 256-bits/cycle.
you meant 128-bits/cycle, right?
You are right, I wrote double the amount of LS units, I will repair It right away.
If anything else is wrong just say it.
I mean 2x64-bit store for 10h or 2x128-bit load. Because 10h can't execute AVX 256 instructions, it can load data in 128-bit chunks.Quote:
Originally Posted by TESKATLIPOKA
This is 128-bits /cycle for stores, or 256-bits/cycle for loads.
In the Bulldozer core(not module), there is 256-bit load + 128-bit store in the same time. With Bulldozer module there is double of that operations.
Bulldozer core can calculate 2 adresses at same time because it has 2 AGU - adress generation units.
Sandy core can do also 2 adress operations at once, because it has 2 L/S AGU. It has slightly different approach for store. SB store unit is attached to scheduler
Yes, per core it has 2 ALU and 2 AGU. I've made detail diagram for Bulldozer module, K10, Nehalem and of course of Sandy Bridge HT core architecture.Quote:
You are right, I wrote double the amount of LS units, I will repair It right away.
If anything else is wrong just say it.
Attachment 118765
BLAH BLAH BLAH .................. :shrug:
drfedja great work, I love these diagrams:). If you don't mind I will link them to another forum I frequently visit.
Quote:
Originally Posted by drfedja
BTW you interpret the Address Generation Units as units for calculate linear addresses as well as INC/LEA values. The Optimization Guide refers them as simple integer exetution units, too (AGLU).
Would you briefly explain what kind of operations can these units execute?
Thanks
I'd be even more thankful if there happened to be a version in English. :p:Quote:
Originally Posted by TESKATLIPOKA
Also I'd like to know what type of instructions can execute AGLU, but what my knowledge of what can AGLU execute is based also on Optimisation Manual and my assumptions is that the AGLU can execute address calculations and LEA, and probably can execute INC. If AMD's manual says that the AGLU can execute simple ALU operations. Maybe i'm wrong for INC, but it could be possible for such unit to support some other type of instructions than CALL and LEA.Quote:
Originally Posted by Oliverda
If it can calculate adress, that unit can also execute simple ADD or INC with unsigned integer (address + offset) and some logical operations like XOR or AND. That is my speculation, because Optimisation Manual probably isn't fully written.
Optimisation guide also refer this:
Optimisation manual says that the AG0|AG1 units execute LEA instruction when work with 3 operands. But with legacy 2 operand instructions LEA can be executed only at EX0|EX1 units. AG0|AG1 can execute CALL instructions, which is double op decoded. Fist op. execute on EX and secon op. execite on AGLU.Quote:
There are four integer execution units per core. Two units which handle all arithmetic, logical and
shift operations (EX). And two which handle address generation and simple ALU operations
(AGLU). Figure 2 shows a block diagram for one integer cluster. There are two such integer clusters
per compute unit.
The CALL instruction clearly transfers control to another procedure, and the RET instruction returns to the instruction following the call.
But that isn't any big difference in comparison to K10. K10 also execute CALL instruction like double op, but on BD CALL disp, near and CALL reg, near has 50% lower latency than 10h and CALL mem (near) is hardwired - double decoded, on 10h is microcoded.
According to Optimisation manual, main difference in BD AGU vs 10h AGU units is that the BD AGU can execute LEA, when work with three operands, and CALL is fully hardwired, with slightly lower latencies.
Use google translate to learn Serbian... ;) :PQuote:
Originally Posted by danielkza
I will translate that diagrams to English, that isn't problem, but I think it is understandable in that version. Picture is worth a thousand words! :P
drfedja awesome looking diagrams, however I think there's a small error for the Bulldozer FPU. Bulldozer only has 1 IMAC unit and it's located in Pipe 0 which it shares with an FMA unit and a convert unit. The two integer units in pipe 2 and pipe 3 are for vector integer ADD(multiplication is done in the IMAC unit) as well as AVX, SSE and x87 instructions that are not handled by the FMA, CVT, or the XBR units.
You are right. I will correct that.
There are no 256-bit integer AVX instructions (256-bit int. AVX comes with AVX2) and integer FMA is handled by FP pipe 0.
According to Optimisation Manual:
All of them can execute integer SIMD instructions. Pipe 0 performs integer fused multiply accomulate, and pipe 1 execute shuffle and FSTORE and all of integer SIMD.Quote:
A 128-bit integer multiply accumulate (IMAC) unit is incorporated into FPU pipe 0. The IMAC
performs integer fused multiply and accumulate, and similar arithmetic operations on AVX, MMX
and SSE data. A crossbar (XBAR) unit is integrated into FPU pipe 1 to execute the permute
instruction along with shifts, packs/unpacks and shuffles. There is an FPU load-store unit which
supports up to two 128-bit loads and one 128-bit store per cycle.
There are four units. According to instruction latencies table, CVT unit is pipe 0, which is shared with FMA0 pipe 0 (128-bit FP block), pipe 1 is XBAR unit which is responsible for shuffling operations and shared with FMA1, pipe 2 and pipe 3 is integer SIMD units which handle some bitwise or logic operations: eg.
ANDNP, ANDNS is FP bitwise operations but it is handled by pipe 2 and pipe 3. That type of instructions has same troughput on 10h, but there is shared with FADD or FMUL pipe.
The thread's becoming more & more technical. I still wonder whether bulldozer could use all of the four FPU unit(128bit*2 fmac+ 128bit*2 mmx) to run superpi.:D
SuperPi uses about 50% of legacy x87 FP operations. Average IPC of SPi is 0.65-0.7 with 10h microcarchitecture. SPi is mixed type of code, and it is very memory depended, because there is alot of memory stack operations. In general, FPU throughput isn't bottleneck for executing SPi. x87 execution of SPi is saturated by inefficiency of 10h memory subsystem (LS-units->L1D->L2->L3 caches). I think that SPi could be much better on BD, but significantly slower than Sandy or even Nehalem.
In general, SPi isn't optimised code for modern parallel SIMD architecture. There aslo could be problem with unaligned memory access, store to load forwarding and data dependencies in order to run code serialized. That is probably the main reason why is Core architecture so superior when runing such unoptimized code.
Thanks, so there is no newer information about AGLUs.
My speculation: if the AGLUs can handle any of the ALU operations, then they must know normal, zero and sign-extended register copy at least, so the instruction table is inaccurate. The additions also must be handled by them and with a slightly more compexity the SUB, NEG, INC, DEC and CMP operations (not the fused compares, just the standalone ones). The logical NOTs, ANDs, ORs, XORs and (not fused) TESTs also requires only a little more simple circuits.
And exaclty these operations are performed by the double-pumped fast ALUs in Netburst, at 4/cycle rate.
Maybe, some people on the Net had speculated that simple ALU or AGLU on BD may handle instructions like 30 years old 6502. :)Quote:
Originally Posted by Oliverda
However, mov, push and call are most frequent instructions in x86 machine code. Also the SUB, NEG, INC, DEC and CMP is often used, so AGLU unit could be very useful.
Attachment 118788
Quote:
Originally Posted by drfedja
I think the MOV section covers simple loads, stores (certain workplace of AGUs) and register copies on the picture. Since the PUSH and POP instructions has been already recuced to single store and load operations at execution level by the K10's Stack Engine, they had to look for another instruction group to speed up (my mentioned conception could extend the general integer execution speed from K10's 3 to 4 ALU operations/cycle/thread). Many conditional jumps (je, jne and others) will be fusioned with preceding TEST/CMP instruction, so the listed add-like and logical ALU instructions would cover another 10-12% on the picture by the AGLU-s.
good idea for cpus that are ONLY expensive since people buying such chips cant really do anything about it. but for chips in the 300-400$ range its going to deter people who dont need the nice heatsink unless they also have the regular versions also available with a discount.Quote:
Originally Posted by Mats
Intel Considers to Bundle Liquid Cooling Solution with Next-Generation Enthusiast ProcessorsQuote:
Originally Posted by Mats
http://www.xbitlabs.com/news/coolers...rocessors.html
That is an interesting concept, but then they have to deal with potential for RMA. Having a fan fail on a inexpensive heatsink isn't the same, or as likely, as having the pump fail on the water-cooling unit. Kind of a cool idea, but I'd be afraid it would come back to haunt them in the long term.
I had Coolit sealed water systems pump pop. It took the whole system except cpu(5870, AM3 motherboard). I would imagine that if AMD went this way, they would use one of those sealed systems as they are cheapest. If a air cooler fails, you have system shut down or freeze, if water cooler fails, you have quite a bit of damage.
all alienware PCs come with these now, so i bet they are reliable enough to use with other products too
would AMD manufacture them or farm them out?
Farm them out. AMD doesn't even manufacture their own CPUs....Quote:
Originally Posted by thematrixhazune
I think, it will be good idea. The topmodel CPU bundled with some better aircooler (Tower type) or lowend WT setup as H50 or H70....
http://www.amdzone.com/phpbb3/viewto...rt=900#p209349
Starting to look like BD is a total dud. Sorry, it hurts me to say this but I believe OBR is correct. :( I just hope I didn't wast $230 CDN on a Crosshair V mobo.
BD = DNF of processors. ???
nice i'll see lots of highend boards going for cheap :D
Ill wait till the end of October before I slowly start losing faith in BD. I hope that day never comes.
If it's true it means there is a problem with yields. It does not mean that BD has bad performance of some sorts.Quote:
Originally Posted by freeloader
If Orb is correct. I'm magical.Quote:
Originally Posted by freeloader
It's capacity problem, which occured with old 90nm X2.Quote:
Originally Posted by muziqaz
I think everyone especially AMD would be happy to sell as much as they did in 90nm days ;)Quote:
Originally Posted by undone
I hope you can show us some tricks then, if not you better start learning some. :) I'm pretty sure he's going to be right about sub-par performance and the actual date you can purchase a CPU (October).
I really hope AMD ditches SOI and just uses a bulk process in the future. SOI has been the thorn in AMD's side for a few years now. Always causing
delays on a new process node.
Sub Par, you mean like in those benches he made up?Quote:
Originally Posted by freeloader
I seen benches from multiple sources now and I can't believe they're all fake. I seriously think BD is a dud. Starting to remind me of the original Phenom launch.
And what are those multiple sources? Everything I know about was from OBR and that Turkey site had just some fake benches from OBR.Quote:
Originally Posted by freeloader
http://www.overclock3d.net/articles/...ces_revealed/1
Can you explain why the price for BD will be 300 dollars when Its performance should be worse than even SB 2500k and is released almost one year later.
On the other hand I can pretty much agree on the date you can buy It. Release date in September with availability in October.
multiple sources :D
you got me :up:
If I told you where I've seen numbers, I would have to kill you. :) I believe what I've seen and as I've said, it does not look good for BD. You can thank me in two months when you see the numbers for yourself.
Why can't you tell us the sources? It shouldn't be too much trouble. I believe you've only seen the OBR benches, which he admitted were fake/troll induced. I've been following this thing for months, and have heard next to nothing on performance figures elsewhere. BD not arriving in vast numbers isn't enough to convince me it's a fail.Quote:
Originally Posted by freeloader
I just wanted to say that. It costs me a dollar. :( LOL.
Go out on the net and find them. You can obviously tell which ones are fake and which ones may have some credibility. I don't believe anything that OBR has published, he's just fishing for page hits. I personally believe AMD has given up trying to take Intel on in a performance per core battle. They can't win that as Intel simply has too much of an advantage in money, R&D and process capability. I'll stick to what I've said and we can check back on this thread in two months. :)Quote:
Originally Posted by PerryR
From what I've seen I'm not worried about bd
if its so obvious, post which you think are real for those of us who dont know which your looking at.
Go find them on the net? Where? I've told you I haven't seen anything aside from OBR, plus, I'm skeptical that you've actually seen such benches; and if you did, they were likely based off OBR's "findings." Furthermore, if AMD is giving up on competitive CPU', why bother with the FX moniker, why bother providing a $300 price tag; why produce a comic that takes blatant shots at Intel? Doesn't add up.Quote:
Originally Posted by freeloader
Freeloader, you know as much as OBR does.
Didn't they change the posting rules here recently? Why are people still spreading FUD?
If I was AMD, I would not put the FX moniker on BD. The comic is merely a marketing tool and a poor one at that. If AMD was so confident in BD, don't you think they would place a lot higher price than $300 on their new CPU?Quote:
Originally Posted by PerryR
More than OBR does. Like I've said, see me in two months.Quote:
Originally Posted by TheBreezyBB
What? Why? Now you're not making sense. You're the one who said BD was going to be a release on the levels of Phenom. Why would AMD price a failed product, that according to you won't compete with Intel's offerings, the same as their competition? Particularly if they aren't confident, or don't have an interest in competing (as you surmise)? That sounds ridiculous.Quote:
Originally Posted by freeloader
But you can't provide your sources. I look forward to seeing your response in the next two months.Quote:
More than OBR does.
Any prediction of how good/bad BD is just speculation...until we have an actual FX chip on our mobo's socket:)
You're the one who said AMD is going to have a $300 dollar price tag on BD, not me. If you had a product that was faster than your competitors, you would definitely charge more for it. We will see in two months who is right and who was wrong. A lot of AMD peeps around here are going to end up with egg on their faces, including myself. I already set up a CHV system with a Phenom II 955 (waiting for BD to arrive when I built it), but now I feel I made a poor decision. :(Quote:
Originally Posted by PerryR
Who says it has to be faster? As long as it matches SB, I'll be more than satisfied.
I honestly don't think most (rational) AMD fans expect BD to crush the 2600K since they're priced in the same range.Quote:
Originally Posted by freeloader
That being said, I expect BD to be quite competetive depending on the workload... If you have a need for a SPi/IPC monster you may well have made a mistake buying the C5F... :yepp:
If your looking for a multi-tasking machine that will be good with modern workloads, I think the C5F was a good purchase, and will only get better when software developers start exploiting the new features....
AMD seems to be concentrating on Performance per Watt, and from what I've seen they're doing a daym good job of it!
I talked to my guy @ MicroCenter today and he said the A3xxx laptops are selling like hotcakes, they're even having a hard time keeping them in stock!
It all comes down to performance per watt, and I don't doubt that BD will kick butt in that department... :up:
I'm impatient too man... Theres been alot of sillyness concernig BD, but I'm not ready to listen to all the BS being rehashed by numerous websites and fake benchmarks... :rolleyes:
Guess we'll all see who was right in the next few weeks... :D
To sum up this last page and a half in three words?
"cool story br0".
I'm not trying to be a troll here, but mindless arguing is mindless arguing. ...over numbers from ES steppings about product unreleased to boot.
I'll see you guys in a month and I'll make sure to buy one of AMD's competitively priced 8 core chips.
Beep is a fanboy... :D
It don't make you bad man...I am too. ;)
I'll shaddup up now... I always drink beer, damn, whiskey! sigh...
I'm not a :banana::banana::banana::banana: folks, sorry for even posting. It doesn't make me bad (hic). :cool:
freeloader BD won't crush SB but will be an excellent competitor that's what we all want. To crush the competition BD would need to have at least a core better by 10% than SB. Even if it had the same core to core performance It would be better only in 5-8 threads because SB has HT. You need to be reminded that SB is better by 30-35% than Deneb core to core and you want BD to have a better core by 40-50% than Deneb thats pretty much unreal.
Because you won't get that much improvement BD is a disappointment for you, then what would you buy, SB? BD should be on par with SB or you can get SB-E but it would be pointless if you don't use more than 4 threaded applications because SB and SB-E will perform almost the same in single thread and only the higher core count will make the real difference.
hm....what can you say me example about multithreads performance against 2500k ....,-)?Quote:
Originally Posted by freeloader
Price about 300$ doesnt mean, performance is whorse than A or B CPU...How many people buy CPU for 500$ or more? Example, sells 1000 pieces of 300$ CPU and only 150 pieces of 500$ CPUs. ANd now, whats better for company as AMD? And second, if 300$ CPU will be cheaper and simillary in performance than 400$ from Intel, doesnt mean from your point of view, its whorse? Thirdly, u have two CPUs, one with 2 cores+ht, very high clocks and second CPU with 6 cores, low clocks. What will be better? AVerage will be this two CPUs simillary, but for gamer user will be better first version, for graphic designer will be better second choice.