Real Temp - New temp program for Intel Core processors

Monstru: RealTemp 3.30 seems to be reading your temperature sensors correctly. It is using TJMax=99C which it must have read from a register within the CPU. I would assume that this new process should run a little cooler than the original Core i7 CPUs. At full load where these sensors tend to be the most accurate, you've got all 4 cores reporting pretty much the same temperature. That looks good. At idle, these CPUs are designed to shut down 3 of the 4 cores depending on your bios C-State settings. If this is going on then having one core slightly hotter than the other 3 wouldn't be unusual either. Run i7 Turbo to see what core is getting the load at idle. All temperature sensors can have some slope error where they become less accurate at idle compared to at TJMax where they are calibrated. I think Core Temp also supports these new CPUs so you can try that program as well.

The original Core i7 sensors were excellent. I don't know if Intel has changed anything. I guess we'll have to wait until there are more retail CPUs tested and Intel finally releases the documentation for these new CPUs.

KURTZ: In MSR 0x19C it reads 0x884D0033. The chart in the Intel docs show what each bit means so I'll convert this to binary to make it a little easier to see and understand.

Code:

8 8 4 D 0 0 3 3 1000 1000 0100 1101 0000 0000 0011 0011 The above lists the lower 32 bits. Bit 31 is on the far left and is set and bit 0 is on the far right. Bit[31] Reading Valid (1) Bit[30..27] Resolution in Degrees Celsius. (0001) = 1C Bit[22..16] Digital Readout. (1001101) = 77 = Distance to TJMax Bit[5] Critical Temperature Status log (1) Bit[4] Critical Temperature Status (1) Bit[1] Thermal Status Log (1) Bit[0] Thermal Status (1)

RealTemp seems to be reading the data from this CPU correctly but there is a problem with the data. The Thermal Status flag, bit[0], is set which means thermal throttling is in progress even though it isn't thermal throttling based on its performance in the SuperPI tests.

Any other Core 2 you check will end in the digits 00 which means that none of the last 8 bits are set. There is a problem with his CPU. These bits should not be set at idle and if his processor ever overheats, it may not be able to function correctly. I'd ask Intel for a new CPU.

Good news then!!! Anyway, if you need any tests with LGA1156 CPU's, drop me a PM and consider it done, I have a bucket of CPU's and MB's here :)

Unclewebb,
i7 Turbo 6.5 shows EIST checked and grayed out. It and C1E are disabled in bios. Is this a bios bug? I am not able to get RMClock to run with Windows 7 x64. One core does throttle to 20 very briefly every few seconds under load.
Thanks, as always.
Gene

edit: After more testing I found that if I actually enable EIST in bios that the multi drops all the way to 12 at idle as it really should. With EIST disabled I get the throttling described above. I am still puzzled about the EIST box being checked in i7 Turbo.

Another thing that controls your multiplier at idle is your Control Panel -> Power Options -> Minimum Processor state. You usually need EIST enabled in the bios for this option to appear.

Try playing around with that. Some bios versions do not correctly disable EIST even when you disable EIST in the bios. I haven't kept track of what board or bios version does what. When testing with i7 Turbo, run as few other monitoring programs as possible. RealTemp 3.30 and CPU-Z should be OK. Let me know anything else you figure out.

According to Intel I originally thought that EIST had to be enabled for the Turbo to work correctly but I've seen some boards where that doesn't seem to be true so :shrug:

I think the bit that I am reading that Intel documents as the EIST bit may not be 100% true on all boards.

EIST, as I said, is disabled in bios. Minimum processor state, though, does appear.
The multiplier at idle with present settings stays at 21. The only time I see it change is when I am stressing the system - I see the momentary drop to 20 on one thread only. It lasts for only about a fourth of a second and reoccurs only every several seconds. Probably not worthy of concern - just makes me curious. I only got on this when I noticed that EIST is checked in i7 Turbo.
To restate, if I enable EIST it drops the multiplier at idle to twelve but when disabled it stays at 21 except briefly to 20 under 100% load. Turbo can be enabled with EIST disabled on this board.
Thanks again

How about Core i5 750 temps? Pretty cool these little buggers :)

http://lab501.ro/wp-content/uploads/...i750-stock.jpg

Monstru: Any temperature comparisons between the new Core i7 CPUs and this Core i5? I think at the same voltage and frequency and if the i7 has hyper threading disabled that the two will probably run at a similar full load temperature. Hopefully the official launch is this week so we can see some more results. The temperature sensors look very consistent. Core 2 has a slight 2C difference but the other 3 cores are very close together during the Cool Down Test. RealTemp 3.30 appears to be reading these correctly. I just need to update the name so it calls it a Core i5 instead of a Core i7. Thanks for posting that.

Kevin - I didn't do a comparison clock/clock, vCore/vCore, HT Off yet, I will do that pretty soon. The pic above si with i750 stock, with references voltages set manually and with stock normal speed. Anyway, I think it is more important how the actual CPU works, with it's normal features (less VID for 860, HT on, higher clock for i860, etc).

What I can say for both is that even with high voltage (1.45) and high clocks, in both cases the real feel temperature of the heatsink and fets is like...a very little warm fish. This things run pretty darn cold :)

Monstru: Is that with stock cooler or what type of cooler you got on that?

Noctua NH-U12P + NM-I3 + Coolink SWIF2-120P @ 1950rpm + AS5

http://lab501.ro/forum/attachment.ph...2&d=1251633334

Unclewebb, we had wondered when I lap my i7 950 if temps would even out between cores or drop any. Lapped it today, started with 200, 400, 800, then 1500. Not really mirror, but smooth and very flat. Took about 45 minutes.
http://img522.imageshack.us/img522/839/lappedi7.jpg

I typically get about .3 to .5C difference in mount to mount with mx2 when I carefully measure amount of tim, used 6mm ball on all (get best temps with 5-7mm balls), so would need to see more than 1C difference to be real difference. (mx2 is very repeatable mount to mount so used that, mx3 is all over the place).

All testing done with large ffts, custom, so stays on same ffts, ran prime for 20 minutes until water was steady state, then collected temp data every 1 second, and constant water temp for averaging. cpu 4.4ghz, all exact same settings.

It is the delta to water cpu numbers that are important ones, since that corrects for small .2 to .4C difference in water temp/ambients run to run.

BEFORE LAPPING:
Mount 1, 71C core avg, 40.8 delta water to cpu.
Mount 2, 71C core avg, 41.1 delta water to cpu.

POST LAPPING:
Mount 1, 71C core avg, 41.1C delta water to cpu.:rofl::rofl:
Rarely get exact same thing on water to cpu delta between mounts, had to laugh. Just happened to get exact same, but clearly lapping made less than .3C to .5C diff, ie undetectable. I was planning on doing second mount post lapping as well....but no point.

When I first started computer after lapping, started to look like temps 2-3C better, but then realize it is just everything cools off since computer was off for couple hours, soon as look at water temp realize no difference. And after 10 mins, water temp is already at steady state, and core temps already the same.

I have now lapped 3 cpus, only 2 really tested well before and after, and got 0C difference both times. But both times I had reasonably flat cpu's to begin with, ie nothing horrid. My heatkiller has mirror finish and flat as far as I can tell, so not wb issue. Also my temp difference core to core are same as pre lapping. I posted the second pre numbers and the post numbers, you can scroll to end and see numbers, the water temp I manually entered, avg of entire string, the cpu temps are avg.

Code:

DATE TIME MHz CPU_0 CPU_1 CPU_2 CPU_3 GPU LOAD% 9/2/2009 18:52:20 4414.84 71 73 71 68 38 100 9/2/2009 18:52:21 4415.62 69 73 70 68 38 100 9/2/2009 18:52:22 4416.06 71 73 72 69 38 100 9/2/2009 18:52:23 4416.06 70 73 71 69 38 100 9/2/2009 18:52:24 4416.06 70 73 71 69 38 100 9/2/2009 18:52:25 4416.06 70 72 72 67 38 100 9/2/2009 18:52:26 4416.06 71 72 71 68 38 100 9/2/2009 18:52:27 4416.06 70 73 71 68 38 100 9/2/2009 18:52:28 4416.06 70 73 72 69 38 100 9/2/2009 18:52:29 4416.06 70 73 72 68 38 100 9/2/2009 18:52:30 4416.06 71 73 71 68 38 100 9/2/2009 18:52:31 4416.06 71 72 72 68 38 100 9/2/2009 18:52:32 4416.06 70 73 72 69 38 100 9/2/2009 18:52:33 4416.06 70 72 71 68 38 100 9/2/2009 18:52:34 4416.06 71 72 72 68 38 100 9/2/2009 18:52:35 4416.06 71 72 71 67 38 100 9/2/2009 18:52:36 4416.06 70 71 71 68 38 100 9/2/2009 18:52:37 4416.06 70 71 71 68 38 100 9/2/2009 18:52:38 4416.06 71 72 72 67 38 100 9/2/2009 18:52:39 4416.06 71 72 71 68 38 100 9/2/2009 18:52:40 4416.06 70 72 72 68 38 100 9/2/2009 18:52:41 4416.06 70 73 71 69 38 100 9/2/2009 18:52:42 4416.06 71 73 71 69 38 100 9/2/2009 18:52:43 4416.06 71 72 72 69 38 100 9/2/2009 18:52:44 4416.06 70 73 72 69 38 100 9/2/2009 18:52:45 4416.06 71 73 72 68 38 100 9/2/2009 18:52:46 4416.06 71 73 72 68 38 100 9/2/2009 18:52:47 4416.06 71 73 72 67 38 100 9/2/2009 18:52:48 4416.06 70 73 71 68 38 100 9/2/2009 18:52:49 4416.06 70 72 72 68 38 100 9/2/2009 18:52:50 4416.06 70 73 70 67 38 100 9/2/2009 18:52:51 4416.06 70 73 71 68 38 100 9/2/2009 18:52:52 4416.06 71 73 72 69 38 100 9/2/2009 18:52:53 4416.06 71 73 72 69 38 100 9/2/2009 18:52:54 4416.06 71 72 71 69 38 100 9/2/2009 18:52:55 4416.06 71 73 72 68 38 100 9/2/2009 18:52:56 4416.06 71 72 72 68 38 100 9/2/2009 18:52:57 4416.06 71 72 71 67 38 100 9/2/2009 18:52:58 4416.06 71 73 72 67 38 100 9/2/2009 18:52:59 4416.06 71 73 72 69 38 100 9/2/2009 18:53:00 4416.06 71 73 72 68 38 100 9/2/2009 18:53:01 4416.06 71 73 72 68 38 100 9/2/2009 18:53:02 4416.06 70 72 71 68 38 100 9/2/2009 18:53:03 4416.06 71 73 72 68 38 100 9/2/2009 18:53:04 4416.06 70 73 72 69 38 100 9/2/2009 18:53:05 4416.06 71 73 72 67 38 100 9/2/2009 18:53:06 4416.06 70 73 71 67 38 100 9/2/2009 18:53:07 4416.06 71 73 70 67 38 100 9/2/2009 18:53:08 4416.06 71 73 72 68 38 100 9/2/2009 18:53:09 4416.06 71 73 72 68 38 100 9/2/2009 18:53:10 4416.06 71 73 72 68 38 100 9/2/2009 18:53:11 4416.06 72 73 72 68 38 100 9/2/2009 18:53:13 4416.06 71 73 72 69 38 100 9/2/2009 18:53:14 4416.06 71 73 72 68 38 100 9/2/2009 18:53:15 4416.06 71 73 72 68 38 100 9/2/2009 18:53:16 4416.06 71 73 72 68 38 100 9/2/2009 18:53:17 4416.06 71 73 72 68 38 100 9/2/2009 18:53:18 4416.06 71 73 72 68 38 100 9/2/2009 18:53:19 4416.06 71 74 71 68 38 100 9/2/2009 18:53:20 4416.06 71 73 71 68 38 100 9/2/2009 18:53:21 4416.06 70 72 72 68 38 100 9/2/2009 18:53:22 4416.06 71 72 72 68 38 100 9/2/2009 18:53:23 4416.06 71 72 71 67 38 100 9/2/2009 18:53:24 4416.06 70 73 72 68 38 100 9/2/2009 18:53:25 4416.06 70 73 72 68 38 100 9/2/2009 18:53:26 4416.06 70 73 71 69 38 100 9/2/2009 18:53:27 4416.06 70 71 71 68 38 100 9/2/2009 18:53:28 4416.06 70 73 71 68 38 100 9/2/2009 18:53:29 4416.06 70 73 71 68 38 100 9/2/2009 18:53:30 4416.06 70 73 72 68 38 100 9/2/2009 18:53:31 4416.06 71 73 72 68 38 100 9/2/2009 18:53:32 4416.06 70 73 71 67 38 100 9/2/2009 18:53:33 4416.06 71 72 71 69 38 100 9/2/2009 18:53:34 4416.06 70 72 72 68 38 100 9/2/2009 18:53:35 4416.06 71 73 72 68 38 100 9/2/2009 18:53:36 4416.06 71 73 71 69 38 100 9/2/2009 18:53:37 4416.06 71 73 72 67 38 100 9/2/2009 18:53:38 4416.06 71 73 72 68 38 100 9/2/2009 18:53:39 4416.06 71 72 72 68 38 100 9/2/2009 18:53:40 4416.06 71 72 72 68 38 100 9/2/2009 18:53:41 4416.06 71 73 72 68 38 100 9/2/2009 18:53:42 4416.06 71 73 71 69 38 100 9/2/2009 18:53:43 4416.06 71 74 72 69 38 100 9/2/2009 18:53:44 4416.06 71 73 72 69 38 100 9/2/2009 18:53:45 4416.06 70 72 71 68 38 100 9/2/2009 18:53:46 4416.06 71 73 71 68 38 100 9/2/2009 18:53:47 4416.06 71 72 72 68 38 100 9/2/2009 18:53:48 4416.06 70 73 71 68 38 100 9/2/2009 18:53:49 4416.06 70 73 72 68 38 100 9/2/2009 18:53:50 4416.06 71 73 72 67 38 100 9/2/2009 18:53:51 4416.06 71 72 71 69 38 100 9/2/2009 18:53:52 4416.06 71 73 72 69 38 100 9/2/2009 18:53:53 4416.06 70 72 71 68 38 100 9/2/2009 18:53:54 4416.06 71 73 71 68 38 100 9/2/2009 18:53:55 4416.06 71 73 72 69 38 100 9/2/2009 18:53:56 4416.06 70 73 71 68 38 100 9/2/2009 18:53:57 4416.06 71 73 72 68 38 100 9/2/2009 18:53:58 4416.06 70 73 71 68 38 100 9/2/2009 18:53:59 4416.06 71 72 72 68 38 100 9/2/2009 18:54:00 4416.06 71 72 71 68 38 100 9/2/2009 18:54:01 4416.06 72 72 72 68 38 100 9/2/2009 18:54:02 4416.06 71 73 72 69 38 100 9/2/2009 18:54:03 4416.06 71 73 72 68 38 100 9/2/2009 18:54:04 4416.06 71 73 72 68 38 100 9/2/2009 18:54:05 4416.06 71 73 72 69 38 100 9/2/2009 18:54:06 4416.06 70 72 72 68 38 100 9/2/2009 18:54:07 4416.06 71 72 71 67 38 100 9/2/2009 18:54:08 4416.06 70 71 72 69 38 100 9/2/2009 18:54:09 4416.06 71 73 71 69 38 100 9/2/2009 18:54:10 4416.06 71 72 72 68 38 100 9/2/2009 18:54:11 4416.06 71 73 71 68 38 100 9/2/2009 18:54:12 4416.06 71 73 72 69 38 100 9/2/2009 18:54:13 4416.06 71 73 72 69 38 100 9/2/2009 18:54:14 4416.06 71 73 68 68 38 100 9/2/2009 18:54:15 4416.06 70 73 72 68 38 100 9/2/2009 18:54:16 4416.06 71 73 72 68 38 100 9/2/2009 18:54:17 4416.06 70 73 72 68 38 100 9/2/2009 18:54:18 4416.06 71 73 72 69 38 100 9/2/2009 18:54:19 4416.06 71 73 71 69 38 100 9/2/2009 18:54:20 4416.06 71 73 71 68 38 100 9/2/2009 18:54:21 4416.06 71 73 71 69 38 100 9/2/2009 18:54:22 4416.06 70 73 72 68 38 100 9/2/2009 18:54:23 4416.06 70 71 71 67 38 100 9/2/2009 18:54:24 4416.06 71 72 72 68 38 100 9/2/2009 18:54:25 4416.06 70 73 72 68 38 100 9/2/2009 18:54:26 4416.06 71 72 71 69 38 100 9/2/2009 18:54:28 4416.06 69 73 72 68 38 100 9/2/2009 18:54:29 4416.06 71 73 71 69 38 100 9/2/2009 18:54:30 4416.06 71 73 72 69 38 100 9/2/2009 18:54:31 4416.06 71 72 72 69 38 100 9/2/2009 18:54:32 4416.06 71 73 72 69 38 100 9/2/2009 18:54:33 4416.06 72 73 72 69 38 100 9/2/2009 18:54:34 4416.06 71 73 71 69 38 100 9/2/2009 18:54:35 4416.06 71 73 72 69 38 100 9/2/2009 18:54:36 4416.06 70 73 71 67 38 100 9/2/2009 18:54:37 4416.06 71 72 72 68 38 100 9/2/2009 18:54:38 4416.06 71 73 71 68 38 100 9/2/2009 18:54:39 4416.06 71 73 72 68 38 100 9/2/2009 18:54:40 4416.06 70 73 71 69 38 100 9/2/2009 18:54:41 4416.06 70 73 72 69 38 100 9/2/2009 18:54:42 4416.06 71 72 72 68 38 100 9/2/2009 18:54:43 4416.06 70 73 72 68 38 100 9/2/2009 18:54:44 4416.06 71 72 72 68 38 100 9/2/2009 18:54:45 4416.06 71 73 72 68 38 100 9/2/2009 18:54:46 4416.06 71 73 72 68 38 100 9/2/2009 18:54:47 4416.06 71 72 72 68 38 100 9/2/2009 18:54:48 4416.06 71 73 72 68 38 100 9/2/2009 18:54:49 4416.06 71 73 72 69 38 100 9/2/2009 18:54:50 4416.06 71 73 71 69 38 100 9/2/2009 18:54:51 4416.06 70 72 72 68 38 100 9/2/2009 18:54:52 4416.06 71 73 72 68 38 100 9/2/2009 18:54:53 4416.06 70 73 71 68 38 100 9/2/2009 18:54:54 4416.06 71 72 72 68 38 100 9/2/2009 18:54:55 4416.06 70 73 72 69 38 100 9/2/2009 18:54:56 4416.06 70 73 71 68 38 100 9/2/2009 18:54:57 4416.06 70 73 72 68 38 100 9/2/2009 18:54:58 4416.06 71 73 71 69 38 100 9/2/2009 18:54:59 4416.06 72 72 72 68 38 100 9/2/2009 18:55:00 4416.06 71 73 72 69 38 100 9/2/2009 18:55:01 4416.06 71 73 72 69 38 100 9/2/2009 18:55:02 4416.06 71 73 72 69 38 100 9/2/2009 18:55:03 4416.06 71 73 72 68 38 100 9/2/2009 18:55:04 4416.06 71 73 72 68 38 100 9/2/2009 18:55:05 4416.06 71 73 72 68 38 100 9/2/2009 18:55:06 4416.06 71 72 71 67 38 100 9/2/2009 18:55:07 4416.06 71 71 72 69 38 100 9/2/2009 18:55:08 4416.06 71 73 72 69 38 100 9/2/2009 18:55:09 4416.06 70 73 72 68 38 100 9/2/2009 18:55:10 4416.06 70 73 72 69 38 100 9/2/2009 18:55:11 4416.06 71 73 72 69 38 100 9/2/2009 18:55:12 4416.06 71 73 72 69 38 100 9/2/2009 18:55:13 4416.06 71 73 72 68 38 100 9/2/2009 18:55:14 4416.06 72 73 72 68 38 100 9/2/2009 18:55:15 4416.06 71 73 71 68 38 100 9/2/2009 18:55:16 4416.06 71 73 72 68 38 100 9/2/2009 18:55:17 4416.06 71 73 72 69 38 100 9/2/2009 18:55:18 4416.06 71 73 72 69 38 100 9/2/2009 18:55:19 4416.06 71 73 72 68 38 100 9/2/2009 18:55:20 4416.06 71 73 72 68 38 100 9/2/2009 18:55:21 4416.06 71 72 72 68 38 100 9/2/2009 18:55:22 4416.06 71 73 72 68 38 100 9/2/2009 18:55:23 4416.06 71 73 72 68 38 100 9/2/2009 18:55:24 4416.06 71 73 72 68 38 100 9/2/2009 18:55:25 4416.06 71 73 72 69 38 100 9/2/2009 18:55:26 4416.06 70 72 67 68 38 100 9/2/2009 18:55:27 4416.06 70 73 71 67 38 100 9/2/2009 18:55:28 4416.06 70 72 71 68 38 100 9/2/2009 18:55:29 4416.06 71 73 72 68 38 100 9/2/2009 18:55:30 4416.06 71 73 71 69 38 100 9/2/2009 18:55:31 4416.06 71 73 72 68 38 100 9/2/2009 18:55:32 4416.06 71 73 72 69 38 100 9/2/2009 18:55:34 4416.06 71 73 72 69 38 100 9/2/2009 18:55:34 4416.06 71 73 72 69 38 100 9/2/2009 18:55:35 4416.06 71 73 72 69 38 100 9/2/2009 18:55:36 4416.06 71 73 72 69 38 100 9/2/2009 18:55:38 4416.06 70 72 71 68 38 100 9/2/2009 18:55:39 4416.06 70 73 72 68 38 100 9/2/2009 18:55:40 4416.06 71 73 72 68 38 100 9/2/2009 18:55:40 4416.06 70 73 72 68 38 100 9/2/2009 18:55:41 4416.06 71 73 72 69 38 100 9/2/2009 18:55:43 4416.06 70 73 72 69 38 100 9/2/2009 18:55:44 4416.06 70 73 72 69 38 100 9/2/2009 18:55:45 4416.06 70 73 72 69 38 100 9/2/2009 18:55:46 4416.06 70 73 72 69 38 100 9/2/2009 18:55:47 4416.06 71 73 72 68 38 100 9/2/2009 18:55:48 4416.06 71 73 71 68 38 100 9/2/2009 18:55:49 4416.06 72 72 72 68 38 100 9/2/2009 18:55:50 4416.06 71 72 72 69 38 100 9/2/2009 18:55:51 4416.06 71 73 72 69 38 100 9/2/2009 18:55:52 4416.06 70 73 72 69 38 100 9/2/2009 18:55:53 4416.06 71 73 71 69 38 100 9/2/2009 18:55:54 4416.06 71 73 72 68 38 100 9/2/2009 18:55:55 4416.06 70 73 71 67 38 100 9/2/2009 18:55:56 4416.06 71 72 72 68 38 100 9/2/2009 18:55:57 4416.06 71 73 72 68 38 100 9/2/2009 18:55:58 4416.06 71 73 72 68 38 100 9/2/2009 18:55:59 4416.06 70 73 72 68 38 100 9/2/2009 18:56:00 4416.06 71 73 72 67 38 100 9/2/2009 18:56:01 4416.06 71 72 71 68 38 100 9/2/2009 18:56:02 4416.06 71 73 72 69 38 100 9/2/2009 18:56:03 4416.06 71 72 72 69 38 100 9/2/2009 18:56:04 4416.06 71 73 72 66 38 100 9/2/2009 18:56:05 4416.06 71 73 72 69 38 100 9/2/2009 18:56:06 4416.06 71 73 71 68 38 100 9/2/2009 18:56:07 4416.06 71 73 72 69 38 100 9/2/2009 18:56:08 4416.06 71 73 71 69 38 100 9/2/2009 18:56:09 4416.06 72 72 73 68 38 100 9/2/2009 18:56:10 4416.06 70 73 71 69 38 100 9/2/2009 18:56:11 4416.06 71 73 72 68 38 100 9/2/2009 18:56:12 4416.06 71 73 72 68 38 100 9/2/2009 18:56:13 4416.06 71 73 72 68 38 100 9/2/2009 18:56:14 4416.06 71 73 72 68 38 100 9/2/2009 18:56:15 4416.06 71 73 71 67 38 100 9/2/2009 18:56:16 4416.06 71 73 72 68 38 100 9/2/2009 18:56:17 4416.06 71 72 72 68 38 100 9/2/2009 18:56:18 4416.06 71 73 72 69 38 100 9/2/2009 18:56:19 4416.06 71 73 72 68 38 100 9/2/2009 18:56:20 4416.06 71 73 72 68 38 100 9/2/2009 18:56:21 4416.06 71 72 72 69 38 100 9/2/2009 18:56:22 4416.06 71 72 72 68 38 100 9/2/2009 18:56:23 4416.06 70 72 71 68 38 100 9/2/2009 18:56:24 4416.06 71 73 71 68 38 100 9/2/2009 18:56:25 4416.06 71 73 72 69 38 100 9/2/2009 18:56:26 4416.06 71 73 72 68 38 100 9/2/2009 18:56:27 4416.06 71 73 72 69 38 100 9/2/2009 18:56:28 4416.06 71 73 72 69 38 100 9/2/2009 18:56:29 4416.06 71 73 72 68 38 100 9/2/2009 18:56:30 4416.06 71 72 72 69 38 100 9/2/2009 18:56:31 4416.06 70 72 72 67 38 100 9/2/2009 18:56:32 4416.06 71 73 72 68 38 100 9/2/2009 18:56:33 4416.06 71 73 72 69 38 100 9/2/2009 18:56:34 4416.06 71 73 72 69 38 100 9/2/2009 18:56:35 4416.06 71 74 71 69 38 100 9/2/2009 18:56:36 4416.06 71 73 72 68 38 100 9/2/2009 18:56:37 4416.06 72 73 72 69 38 100 9/2/2009 18:56:38 4416.06 71 73 72 68 38 100 9/2/2009 18:56:39 4416.06 70 72 71 67 38 100 9/2/2009 18:56:40 4416.06 71 73 72 68 38 100 9/2/2009 18:56:41 4416.06 71 73 72 68 38 100 9/2/2009 18:56:42 4416.06 71 73 72 68 38 100 9/2/2009 18:56:43 4416.06 71 73 72 69 38 100 9/2/2009 18:56:44 4416.06 71 73 72 69 38 100 9/2/2009 18:56:45 4416.06 71 72 72 68 38 100 9/2/2009 18:56:46 4416.06 70 72 72 68 38 100 9/2/2009 18:56:47 4416.06 70 73 72 68 38 100 9/2/2009 18:56:48 4416.06 70 73 71 68 38 100 9/2/2009 18:56:49 4416.06 70 73 71 69 38 100 9/2/2009 18:56:50 4416.06 71 73 72 69 38 100 9/2/2009 18:56:52 4416.06 71 73 72 69 38 100 9/2/2009 18:56:53 4416.06 71 73 72 69 38 100 9/2/2009 18:56:53 4416.06 71 73 71 68 38 100 9/2/2009 18:56:55 4416.06 71 72 72 67 38 100 9/2/2009 18:56:56 4416.06 71 73 72 67 38 100 9/2/2009 18:56:57 4416.06 71 74 72 69 38 100 9/2/2009 18:56:58 4416.06 70 73 71 69 38 100 9/2/2009 18:56:59 4416.06 71 73 72 68 38 100 9/2/2009 18:57:00 4416.06 71 73 71 68 38 100 70.84927798 29.75 41.09927798

post lapping temp

Code:

DATE TIME MHz CPU_0 CPU_1 CPU_2 CPU_3 GPU LOAD% 9/2/2009 20:47:30 4416.09 71 73 72 68 38 100 9/2/2009 20:47:31 4416.09 70 73 72 68 38 100 9/2/2009 20:47:32 4416.09 71 73 72 68 38 100 9/2/2009 20:47:33 4416.09 70 73 72 69 38 100 9/2/2009 20:47:34 4416.09 70 73 72 69 38 100 9/2/2009 20:47:35 4416.09 71 72 71 67 38 100 9/2/2009 20:47:36 4416.09 71 73 72 67 39 100 9/2/2009 20:47:37 4416.09 70 73 71 68 38 100 9/2/2009 20:47:38 4416.09 70 72 71 68 38 100 9/2/2009 20:47:39 4416.09 71 73 71 68 39 100 9/2/2009 20:47:40 4416.09 70 73 71 68 39 100 9/2/2009 20:47:41 4416.09 70 73 71 69 38 100 9/2/2009 20:47:42 4416.09 71 73 72 68 39 100 9/2/2009 20:47:43 4416.09 70 73 70 69 39 100 9/2/2009 20:47:44 4416.09 70 72 71 69 38 100 9/2/2009 20:47:45 4416.09 71 73 71 68 39 100 9/2/2009 20:47:46 4416.09 70 72 71 68 39 100 9/2/2009 20:47:47 4416.09 70 73 71 69 39 100 9/2/2009 20:47:48 4416.09 71 73 71 68 39 100 9/2/2009 20:47:49 4416.09 70 73 71 68 39 100 9/2/2009 20:47:50 4416.09 71 73 71 68 38 100 9/2/2009 20:47:52 4416.09 71 72 72 68 38 100 9/2/2009 20:47:53 4416.09 70 73 71 68 38 100 9/2/2009 20:47:53 4416.09 70 73 72 68 38 100 9/2/2009 20:47:55 4416.09 71 73 72 68 38 100 9/2/2009 20:47:56 4416.09 70 73 71 68 38 100 9/2/2009 20:47:57 4416.09 71 73 72 67 39 100 9/2/2009 20:47:58 4416.09 70 73 71 67 38 100 9/2/2009 20:47:59 4416.09 71 73 71 68 39 100 9/2/2009 20:48:00 4416.09 70 73 72 69 38 100 9/2/2009 20:48:01 4416.09 70 73 71 68 38 100 9/2/2009 20:48:02 4416.09 71 72 71 68 38 100 9/2/2009 20:48:03 4416.09 71 73 71 69 39 100 9/2/2009 20:48:04 4416.09 69 72 70 68 38 100 9/2/2009 20:48:05 4416.09 71 73 72 68 38 100 9/2/2009 20:48:06 4416.09 70 73 70 68 38 100 9/2/2009 20:48:07 4416.09 70 74 71 68 38 100 9/2/2009 20:48:08 4416.09 71 73 71 68 38 100 9/2/2009 20:48:09 4416.09 70 73 72 68 38 100 9/2/2009 20:48:10 4416.09 71 73 71 68 38 100 9/2/2009 20:48:11 4416.09 71 73 71 68 38 100 9/2/2009 20:48:12 4416.09 70 74 71 68 38 100 9/2/2009 20:48:13 4415.65 71 73 72 69 38 100 9/2/2009 20:48:14 4415.65 71 73 72 68 38 100 9/2/2009 20:48:15 4416.09 70 73 71 68 38 100 9/2/2009 20:48:16 4416.09 71 72 72 67 38 100 9/2/2009 20:48:17 4416.09 71 72 71 67 38 100 9/2/2009 20:48:18 4416.09 70 72 70 68 38 100 9/2/2009 20:48:19 4416.09 71 73 72 68 38 100 9/2/2009 20:48:20 4416.09 70 73 71 68 38 100 9/2/2009 20:48:21 4416.09 71 73 71 68 38 100 9/2/2009 20:48:22 4416.09 71 73 71 68 38 100 9/2/2009 20:48:23 4416.09 70 71 71 68 38 100 9/2/2009 20:48:24 4416.09 71 73 71 69 38 100 9/2/2009 20:48:25 4416.09 70 73 71 69 38 100 9/2/2009 20:48:26 4416.09 70 73 71 69 38 100 9/2/2009 20:48:27 4416.09 71 73 72 68 38 100 9/2/2009 20:48:28 4416.09 70 73 71 69 38 100 9/2/2009 20:48:29 4416.09 70 72 72 69 38 100 9/2/2009 20:48:30 4416.09 70 71 72 67 38 100 9/2/2009 20:48:31 4416.09 71 73 71 68 38 100 9/2/2009 20:48:32 4416.09 70 73 71 69 38 100 9/2/2009 20:48:33 4416.09 70 73 71 68 38 100 9/2/2009 20:48:34 4416.09 70 74 71 69 38 100 9/2/2009 20:48:35 4416.09 71 73 71 68 38 100 9/2/2009 20:48:36 4416.09 70 72 70 68 38 100 9/2/2009 20:48:37 4416.09 71 72 72 68 38 100 9/2/2009 20:48:38 4416.09 70 73 71 67 38 100 9/2/2009 20:48:39 4416.09 71 73 71 68 38 100 9/2/2009 20:48:40 4416.09 71 73 71 67 38 100 9/2/2009 20:48:41 4416.09 71 73 71 68 38 100 9/2/2009 20:48:42 4416.09 71 73 72 68 38 100 9/2/2009 20:48:43 4416.09 71 73 71 69 38 100 9/2/2009 20:48:44 4416.09 71 73 71 69 38 100 9/2/2009 20:48:45 4416.09 70 72 71 68 38 100 9/2/2009 20:48:46 4416.09 71 72 72 68 38 100 9/2/2009 20:48:47 4416.09 71 73 71 69 38 100 9/2/2009 20:48:48 4416.09 70 73 71 68 38 100 9/2/2009 20:48:49 4416.09 70 73 71 68 38 100 9/2/2009 20:48:50 4416.09 70 73 71 68 38 100 9/2/2009 20:48:51 4416.09 70 73 70 69 38 100 9/2/2009 20:48:52 4416.09 70 72 71 68 38 100 9/2/2009 20:48:53 4416.09 71 71 71 67 38 100 9/2/2009 20:48:54 4416.09 70 72 71 68 38 100 9/2/2009 20:48:55 4416.09 71 73 68 68 38 100 9/2/2009 20:48:56 4416.09 70 73 67 69 38 100 9/2/2009 20:48:57 4416.09 71 73 71 68 38 100 9/2/2009 20:48:58 4416.09 71 73 71 68 38 100 9/2/2009 20:48:59 4416.09 70 73 71 69 38 100 9/2/2009 20:49:00 4416.09 70 73 71 68 38 100 9/2/2009 20:49:01 4416.09 70 73 71 68 38 100 9/2/2009 20:49:02 4416.09 70 73 71 69 38 100 9/2/2009 20:49:04 4416.09 71 73 72 69 38 100 9/2/2009 20:49:05 4416.09 70 73 70 69 38 100 9/2/2009 20:49:05 4416.09 70 73 72 69 38 100 9/2/2009 20:49:07 4416.09 70 73 71 68 38 100 9/2/2009 20:49:08 4416.09 70 73 72 69 38 100 9/2/2009 20:49:09 4416.09 70 73 71 68 38 100 9/2/2009 20:49:10 4416.09 70 72 71 69 38 100 9/2/2009 20:49:11 4416.09 71 73 71 68 38 100 9/2/2009 20:49:12 4416.09 70 73 72 68 38 100 9/2/2009 20:49:13 4416.09 70 73 72 68 38 100 9/2/2009 20:49:14 4416.09 70 73 71 68 38 100 9/2/2009 20:49:15 4416.09 70 73 71 68 38 100 9/2/2009 20:49:16 4416.09 70 72 72 68 38 100 9/2/2009 20:49:17 4416.09 70 72 72 68 38 100 9/2/2009 20:49:18 4416.09 70 73 71 68 38 100 9/2/2009 20:49:19 4416.09 70 72 71 68 38 100 9/2/2009 20:49:20 4416.09 70 73 72 67 38 100 9/2/2009 20:49:21 4416.09 70 74 71 68 38 100 9/2/2009 20:49:22 4416.09 70 73 72 69 38 100 9/2/2009 20:49:23 4416.09 69 73 71 68 38 100 9/2/2009 20:49:24 4416.09 70 73 72 69 38 100 9/2/2009 20:49:25 4416.09 70 73 71 68 38 100 9/2/2009 20:49:26 4416.09 70 71 72 68 38 100 9/2/2009 20:49:27 4416.09 70 72 71 68 38 100 9/2/2009 20:49:28 4416.09 70 73 72 67 38 100 9/2/2009 20:49:29 4416.09 71 73 72 69 38 100 9/2/2009 20:49:30 4416.09 70 73 71 68 38 100 9/2/2009 20:49:31 4416.09 70 73 72 68 38 100 9/2/2009 20:49:32 4416.09 70 72 70 67 38 100 9/2/2009 20:49:33 4416.09 70 72 71 67 38 100 9/2/2009 20:49:34 4416.09 70 71 71 68 38 100 9/2/2009 20:49:35 4416.09 70 73 71 68 38 100 9/2/2009 20:49:36 4416.09 70 73 72 68 38 100 9/2/2009 20:49:37 4416.09 70 73 72 68 38 100 9/2/2009 20:49:38 4416.09 70 73 71 69 38 100 9/2/2009 20:49:39 4416.09 71 73 72 68 38 100 9/2/2009 20:49:40 4416.09 71 73 71 68 38 100 9/2/2009 20:49:41 4416.09 70 73 72 68 38 100 9/2/2009 20:49:42 4416.09 70 73 71 69 38 100 9/2/2009 20:49:43 4416.09 71 73 72 68 38 100 9/2/2009 20:49:44 4416.09 70 72 72 69 38 100 9/2/2009 20:49:45 4416.09 70 73 71 68 38 100 9/2/2009 20:49:46 4416.09 70 73 72 69 38 100 9/2/2009 20:49:47 4416.09 71 73 71 68 38 100 9/2/2009 20:49:48 4416.09 70 73 72 68 38 100 9/2/2009 20:49:49 4416.09 70 73 71 69 38 100 9/2/2009 20:49:50 4416.09 70 72 70 68 38 100 9/2/2009 20:49:51 4416.09 70 72 72 68 38 100 9/2/2009 20:49:52 4416.09 70 72 72 68 38 100 9/2/2009 20:49:53 4416.09 71 73 72 68 38 100 9/2/2009 20:49:54 4416.09 70 73 72 68 38 100 9/2/2009 20:49:55 4416.09 70 73 72 68 38 100 9/2/2009 20:49:56 4416.09 71 73 72 68 38 100 9/2/2009 20:49:57 4416.09 70 73 71 68 38 100 9/2/2009 20:49:58 4416.09 70 73 72 69 38 100 9/2/2009 20:49:59 4416.09 71 73 72 69 38 100 9/2/2009 20:50:00 4416.09 70 73 72 69 38 100 70.63590604 29.56 41.07590604

rge: Thanks for your thorough testing. After your marathon last month of block remounting and heat paste testing, I don't have any trouble believing your numbers. Nice to see your consistent results when using RealTemp.

I lapped my E8400 last month and the results were very similar. It looked nice but there was no noticeable change in core temperature. I think you need a seriously messed up IHS before you see any dividends from lapping.

I think your testing also proves that the difference in temperature from core to core on an i7 has nothing to do with thermal paste and how it was applied or how square the IHS is. It just happens.

Quote:

Originally Posted by unclewebb

I think you need a seriously messed up IHS before you see any dividends from lapping.

You don't have to think that anymore ;)

Hey unclewebb,
I left a message on your visitor page, I hope you can take a look.

Aside from that, I was wondering if you intend to implement separate GPU temp readings for multi-GPU systems. Well, I'm on the NVIDIA camp for now so I'm particularly interested in your plans for SLI setups... Thanks!

hi Uncle like you can see there is a trouble with you latest beta ...

http://www.hwupgrade.it/forum/showpo...5&postcount=79

ps. thanks for your support :)

Hopefully that screen shot is version 3.30 RC12. There's a big bug in that version so I pulled it after less than a day but lots of sites without my permission decided to mirror it anyhow. I haven't heard of any complaints about RC11 so ask testers to give that version a try.

RealTemp 3.30 RC11
http://www.fileden.com/files/2008/3/...alTempBeta.zip

Hopefully in the near future I will get back to working on RealTemp and add correct support for the new Core i5 and i7.

theGryphon: RealTemp does sort of support SLI. It samples the temperature of each GPU and then reports the highest temperature. I might add individual temperatures in the future. I sent you a PM about your questions. Send me some more info so I can help you out.

Quote:

Originally Posted by unclewebb

RealTemp 3.30 RC11
http://www.fileden.com/files/2008/3/...alTempBeta.zip

Hopefully in the near future I will get back to working on RealTemp and add correct support for the new Core i5 and i7.

and remember to put the vid min/max option like the older versions ... :p

So is realtemp accurate for i7?

I'd trust RealTemp and Core Temp 0.99.5 before I'd trust any other temperature monitoring program. I could give you a list of programs that are either not reporting all cores when hyper threading is enabled, reporting temperatures from the wrong cores or not correctly reading TJMax which is written into each Core i7 CPU. Instead of a biased list, here's a simple test. Run Prime 95 Small FFTs for about 10 or 15 minutes until your temperatures have stabilized. Now start comparing temperature programs. Post some results and I'll show you what I'm talking about.

Suggestion

Realtemp rocks however it would be perfect if it could support display of multiple GPU temps, not just the first one it finds (for more than 1 gpu installed, eg SLI systems).

Thanks,
Niz

justniz: When using SLI, RealTemp samples all GPUs and reports the highest temperature. This should work with 3 way SLI too but I haven't tested that yet.
I thought the hottest temperature would be more important to a user than just reporting the first GPU it finds.

I think justniz is suggesting the same thing as I did: reporting each and every GPU in the system. I think this would be just perfect! ;)

are those sensors correct ? i cant understand how this think works :p

http://img406.imageshack.us/img406/9608/shot0001n.jpg

Core0 (a little) and Core1 (definitely) looks stuck at 37°C but they works OK in load so no problems.
BTW nice temps in LinX. :up:

thanks m8 :) i used to get lower temps with some peltiers but i removed them today :)