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The favour is to yourself. If you are not polite, it reflects poorly on both yourself and your message. Rudeness is often an attempt to add the illusion of strength to a weak message, and people tend to treat it as such. If you are speaking the truth, it is best to be civil.Quote:
Originally Posted by savantu
I know this post is off-topic, but in this thread (and others) it seems relevant.
Hmm, looks like K8 does prefetch data from the RAM:
http://www.cpuid.com/reviews/K8/index.phpQuote:
The K8 also includes an hardware prefetch logic, that allows to get data from memory to the L2 cache during the the memory bus idle time.
Not prefetching is just stupid. Simple prefetching is rediculously easy to implement, just like a victim cache. It's large gains for very little work and cost (die size, etc). Therefore, I call bogus on the "no prefetching" statement.
Something I started wondering recently. After watching what nvidia pulled off with their G80, who's to say AMD isnt' doing the same thing. Is there any reputable evidence that says all that 65nm is, is a shrink with no improvements?
disclamer:
(they're may be, i don't know)
Yes, AMD themselves have said time and time again that the new core™ is to debut in the second half of the next year.Quote:
Originally Posted by flippin_waffles
This thread just made me think of something: We still haven't seen any rev G CPUs, despite them being out in just a few days! What are the chances that AMD is as tight with rev H as rev G? Could be a long wait...
It's really very unusual for a product to be kept under such secrecy as rev G has been. It's kind of strange, as the CPUs really don't seem to be more than die shrinks.
Quote:
Originally Posted by Mikael
That's what I mean. They seem to be, but i wasn't aware of any concrete evidence that says that is all they are. I never realized that AMD themselves iterated this, so thanx!
The avaliblity of ES samples depends alot on whos gonna use them.
If 65nm K8s can be plugged into a MB without a BIOS update and all VRM is fine. Then there is no need for AMD to make alot of ES samples and distribute to OEMs and MB makers. Another option is also that 65nm K8s aint ready yet, or just become ready and is very thight with any form of avaliblity.
Actually, I think AMD started mass production several months back. I think I read it in an interview with an AMD employee.Quote:
Originally Posted by Shintai
There have been 65nm CPUs kickng around for AGES..fact. S7 had a couple on 939 to test some early ideas for AMD (before AM2)
AFAIK, yeilds are good on 65nm coz they`ve had a while to get everything just the way they want it. I reckon a few memory controller tweaks to test ideas for K8L.
If people are banding about ideas on other reasons for 65nm being so quiet because its more than just a die-shrink, I have my own conspiracy theory that no-one wants to hear. ;)
If its just a die-shrink, I agree with the "ES arent needed en masse" idea
i want to add something about the X4. I call the AMD quad core X4 because K8L is a name from intel, and i prefer the AMD real name, misteriously don't exist.
I called the AMD press service and the chip is called Quad core. X4 to make more short.
I want to add some informations about X4.
I have seen that the L3 is half exlusive. ( and half inclusive ) with L1D/I ( don't remember it was L1D or L1I :cry: )
There is two revision of X4. A0 still have some bugs with decoders, and A1 is perfect ( theinquirer )
X4 have 4 complexe decoders. ( K8 3 simple 1 complexe )
The whole chip have been revised.
To people who want know what about Quad Fx platforme ( 4x4 ) CPU are not 65nm, i will answer that there is no brisbane with 1024ko of L2. Windsor 90nm, the core taked for 4x4 is 1024ko.
3.5ghz overclock is possible in deed. I want to remerber you the 130nm=>90nm transition. AMD go 2.2ghz K8 to 3Ghz today Fx74.
The 90nm san diego was the revision witch was the one who give the overclock easy with AMD K8.
Actual 90nm is SOI DSL. The 65nm is SiGe.
SiGe is used for hyperfrequency hardware. AMD tell us that the 65nm will give 42% improvement about the transistors.
Imagine 42% more that 2.8ghz-3ghz => 3.9ghz-4.26ghz ^^
I don't really think that AMD will do that incredible achievement. But i realy think that brisbane will clock easy @3.5ghz-3.6ghz like conroe.
I want to remember that Brisbane is not a die shrink. Brisbane can do 0.5 multiplier. The 5 dec 06 AMD will release some models on 65nm.
I want to spot light on the P rating about the Brisbane.
4400+ 65nm : 2.3ghz 512ko*2
4400+ 90nm : 2.2ghz 1024ko*2
4800+ 65nm : 2.5ghz 512ko*2
4800+ 90nm : 2.4ghz 1024ko*2
+100mhz = cut 512ko
4200+ 90nm : 2.2ghz 512ko*2
4000+ 65nm : 2.1ghz 512ko*2
The 4000+ have 100mhz less and loose 200+
in single core 512ko/1024ko are 300+
in dual core 90nm 512ko/1024ko are 200+
in dual core 65nm 512ko/1024ko is +100mhz
These P ratings are very curious ...
Next i don't have any information about K10, but i speculate that AMD will use to make his K10. I recomand every body of you to see very attentively Fusion and GPGPU. I think i have found the secret of the reverse hyper threading.
X4 is better core.
K10 is reverse hyperthreading with more cores and a new internal bus.
i may have too said ... :woot:
Excuse my very strange language :D
1) ALL K8 have 3 complex Decoders, only conroe has 1 Complex and 3 simple
2) can be exclusive or inclusive, it would be inefficient to do both
3) Half multis and half dividers are going to seriously improve AMD memory performance.
4) expanded Divider options will allow even higher memory Ram (yes of I am speaking of a divider of 2 :D )
5) increasing L1 bandwidth will allow AMD to be the first Company to fetch 32 byte blocks (double that of Conroe) Meaning that its issue rate is far less constrained than Intel's in theory allowing far greater performance.
Sure in Theory Conroe can under Ideal circumstances is able to execute 5 instructions, but only if the instructions are less than 4bytes large on average
i may confused :p:Quote:
Originally Posted by nn_step
Scienta's Blog :Quote:
2) can be exclusive or inclusive, it would be inefficient to do both
AMD's L3 is also more complex than I had thought. I had expected the L3 to be exclusive but AMD has apparently decided to make it more complex. They use it exclusively with data but can use it inclusively with instructions. This is a big improvement and would tend to negate most of Intel's advantage with inclusive cache and its advantage with the shared L2. However, this multi-mode function allows AMD to retain its current cache size flexibility. It would be able to change the size of both L2 and L3 without a severe penalty in performance. Intel does not have this flexibility. Further, Intel's use of shared L2 leaves the processor vulnerable to cache thrashing where one thread pushes instructions out of the L2 only to have its own instructions pushed out by the first thread in a cpu clock wasting tug of war.
i think his right
you're rightQuote:
3) Half multis and half dividers are going to seriously improve AMD memory performance.
Explain a bit more please :p:Quote:
4) expanded Divider options will allow even higher memory Ram (yes of I am speaking of a divider of 2 :D )
Don't think Brisbane have 32byte fetch :stick:Quote:
5) increasing L1 bandwidth will allow AMD to be the first Company to fetch 32 byte blocks (double that of Conroe) Meaning that its issue rate is far less constrained than Intel's in theory allowing far greater performance.
Sure in Theory Conroe can under Ideal circumstances is able to execute 5 instructions, but only if the instructions are less than 4bytes large on average
Brisbane has 128bit (or 16Byte) fetch but the logic for supporting 32byte fetch is includedQuote:
Originally Posted by madcho
interesting ;)Quote:
Originally Posted by nn_step
32Byte instruction fetch will only be possible in K8L, cause is has 256bit L1 cache bus.
K8L decoders are faster than K8's, the 3 of them can decode complex instructions in 1 cicle (2 cicles in K8).
Conroe has 1 slow/complex and 3 fast/simple decoders, but the fast decoders can handle SSE instructions.
Can anyone confirm if rev G ou H have half memory dividers ?
This would finally allow setting the exact clock frequency for almost every cpu/ram frequency.
X4 have four decoders, i saw it on the die shot. It's very clear, we can see 4. :toast:Quote:
Originally Posted by doompc
I think the memory controller will be a bit better in the new 65nm k8 since Amd seems to improve the mem controller in each revision:D
Im waiting for 65nm
And for k10 Barcelona
It seems very promising:toast:
geez somebody leak some ES already! AMD is killing me with this silent treatment. It's like seeing tumbleweed rolling through here the past couple months..
Those 2 CPUs (ADV4_00) were low power 90nm models...Quote:
Originally Posted by K404
you think so? why hold an NDA over details for just that? Low-power 90nm would be like the EE chips we see now.... nothing special, just take a good stepping and knock the voltage down. :)
There are two memory controller ont the X4 :stick: we can see it on the die shot :woot:Quote:
Originally Posted by Teroedni
two dual channel Memory controllers with support for DDR2 and DDR3Quote:
Originally Posted by madcho
K404,
You didn't happen to mean this thread?
Does it have 2 64 bit memory controllers that support both DDR2 and DDR3 or 1 dual channel DDR2 and 1 dual channel DDR3 controller?