Ok, I didn't get any answers to most of my previous questions yet so far. But maybe I'll still get some of them answerred, who knows. I'll just await and see what happens. When it's about using a turbo-pll to externally feed the PCI-E and SATA: I'm currently examinating the data sheet and feature list of the ICS954119 clock generator;
Datasheet: http://www.icst.com/datasheets/ics954119.pdf
Feature list: http://www.icst.com/icscs/PartSummar...119&mode=short
According to the datasheet, there are several pins on the clockgerator that are related to the PCI-E and SATA functions:
PCI-E:
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Pin # |Pin name |Pin type |Description
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17___|PCIEXT0 |___OUT__|True clock of differential PCI_Express pair.
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18___|PCIEXC0 |___OUT__|Complement clock of differential PCI_Express pair.
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19___|VDDPCIEX|__PWR__|Power supply for PCI Express clocks, nominal 3.3V
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21___|PCIEXT1 |___OUT__|True clock of differential PCI_Express pair.
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22___|PCIEXC1 |___OUT__|Complement clock of differential PCI_Express pair.
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23___|PCIEXT2 |___OUT__|True clock of differential PCI_Express pair.
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24___|PCIEXC2 |___OUT__|Complement clock of differential PCI_Express pair.
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30___|PCIEXC3 |___OUT__|Complement clock of differential PCI_Express pair.
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31___|PCIEXT3 |___OUT__|True clock of differential PCI_Express pair.
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32___|PCIEXC4 |___OUT__|Complement clock of differential PCI_Express pair.
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33___|PCIEXT4 |___OUT__|True clock of differential PCI_Express pair.
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34___|VDDPCIEX|__PWR__|Power supply for PCI Express clocks, nominal 3.3V
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SATA:
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Pin # |Pin name |Pin type |Description
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26___|SRCCLKT |___OUT__|True clock of differential pair for S-ATA support.
_____|________|_________|+/- 300ppm accuracy required.
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27___|SRCCLKC |___OUT__|Complement clock of differential pair for S-ATA
_____|________|_________|support. +/- 300ppm accuracy required.
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28___|VDDSRC_|___PWR__|Supply for SRC clocks, 3.3V nominal
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Now what I don't quite understand yet from the data sheet and featurelist:
1. What is meant with "differential pair" when it's about the PCI-E and SATA?
2. What is the difference between the "true" and "complement" clocks?
3. What is meant with "tight ppm accuracy clocks for Serial-ATA"?
Or: what is "ppm"?
4. What is "undriven differential CPU, SRC pair in PD# for power management."?
Also and in the first place: would it lead to any problems I'd have to find a solution for, if I externally feed the PCI-E and SATA continuously with 100MHz, seperated from the FSB, PCI-E and SATA frequencies values that have been set in BIOS? And/or would I still have to set the PCI-E according to the formula FSB = 2.2 * PCI-E in order to let the clock generator / BIOS / motherboard "think" that the PCI-E frequency would have been set to the "correct" value? I hope there's still people around here, that have been working with turbo-pll's back in the days when motherboards didn't have PCI/AGP locks yet... If there's still some of those people around, then I'd hereby like to ask to those people themselves: PLEASE help me, your knowledge, experiences and skills might get very useful to me and other P4GD1 and maybe also P4GPL-X owners who might want to consider a turbo-pll mod for their motherboards. I have a feeling that I don't have to create a complex kind of turbo-pll, probably I can even just use a pll sawed out of an old motherboard. But I just need to know a few things before actually creating it, in order to prevent failure and damage to the motherboard and so on. Thanks very much for ANYTHING that might get useful. :)