AMD K8L ES coming in December

Quote:

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Originally Posted by MAS

K8L cores were renamed
Athlon 64 FX -> Altair FX -> Agena FX;
Athlon 64 X4 -> Altair -> Agena;
Athlon 64 X2 -> Antares -> Kuma

no stars in roadmaps ))))

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I thought those were just 65nm A64 and not K8L :confused:

any info if i coul get an altair based cpu for around U$550~U$700? in q3/2007 (sorry 4 my bad english)

ummm......you will need a Crystal Ball to answer that :D

I think your all full of :banana::banana::banana::banana:.

No one knows how the K8L will perform. So unless you're a x86 cpu engineer sit down and shut the fruck up.

Please don't compare OCed to stock either.. You can't compare the two. You also have no idea how k8L 65nm process is? How can you make such wild claims that Intel 65nm is so much holier then thou. Their sure is a lot of insecurity on this forum its just a constant e-penis orgy.

I will admit I am a fan boy, been using AMD for a long time I never really had any problems and for a long time they were better then Intel, so I stuck with them. Plus I really hated the Netburst architecture.

Also doesn't AMD use the SOI process as well where as Intel doesn't?

Its only 3 months off from q1 so sit tight don't get your panties in a bunch and enjoy the current product that you own.

Also guys calm down, its not like enthusiasts matter that much. AMD is now happy because of Dell, Dell pushes crap load of PC's to people. Most of them don't know or don't care what setup gives them an extra second in the 1 mil superpi bench.

I remember reading a little snipit of why there is no K9 its because K9 stands for Dog.. Would you like your flagship product be named dog..

http://xs208.xs.to/xs208/06442/CONROE-L-NOR.JPG 512kb Stock
http://forum.pcstats.com/showthread.php?t=37608 VS 4mb Stock
http://xs208.xs.to/xs208/06442/266-pi1m.JPG VS 4mb 3.1ghz

This proves conroe is cache dependent and since this is a single threated benchmark the difference between having 2 cores and one in Super pi doesn't exist. A single core AMD scores the same in super PI just as a dual core does because only one core is used so this supports my statment super pi and conroe are made for eachother. With out the cache conroe would be no better then K8's arc wise. The rest is just a gimmic. Its real performance comes from having a insane amount of cache. In the real world it means nothing why AMD's act the same as conroes in performance because most can't tell or see the difference. Conroe was made to bench and its performance doesn't exist in the real world like its hyped in benchmarks because the cache is the main reason for such high scores in super pi but isn't reflected in every benchmark for a reason. Its also not reflected in the real world because most programs will not use all of the cache in the same way the benches do it was made for. In the real world the benches just don't add up for standard use as a system your just not going to see it in everyday things you do. Specially because of the FSB limit.

K8L may use this in a similar way to get more performance by loading stuff way before its calculated with the help of L3 like conroe's large cache size K8L may feel much faster because it uses this trick to make itself feel faster by processing something far ahead of time wile its already loaded into cache afterwords. The more cache you have at this level usouly makes a big difference in performance but not the case with AMD in the past with K8's. Yet I beleave the cache may effect K8L more like Conroe does since its similar with large sizes of cache. Having L3 should make it feel much faster yet I could be wrong because it could be similar to K8's in that way and cache may not matter at all. But hyper transport would accelerate this effect it may help. If intel could do hyper transport then AMD would be in trouble. But since CSI will never come out before HT4 they don't have a chance in hell with FSB agenst K8L until 2009 with CSI-2. By then K11 will be out on 45nm going to 32nm with SOI-4 and 5.

AMD uses Victim Cache policy, it doesn't prefetch data like Conroe's cache.
Seems like K8L's L3 cache won't do it too, but because it wil be shared amog all CPUs, it will be a great help in multi-threaded applications.

btw, Opteron 2222s are sampling for production @ 65nm. they are 3.0ghz parts. :)

dave

Please tell us more..about everything Dave:D

i doubt that dave could tell us much more being under nda like he is

Quote:

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Originally Posted by doompc

AMD uses Victim Cache policy, it doesn't prefetch data like Conroe's cache.
Seems like K8L's L3 cache won't do it too, but because it wil be shared amog all CPUs, it will be a great help in multi-threaded applications.

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Quote:

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Originally Posted by Wiki

A victim cache is a cache used to hold blocks evicted from a CPU cache due to a conflict or capacity miss. The victim cache lies between the main cache and its refill path, and only holds blocks that were evicted from that cache on a miss. This technique is used to reduce the penalty incurred by a cache on a miss.

The original victim cache on the HP PA7200 was a small, fully-associative cache. Later processors, such as the AMD K7 and Intel Netburst, used the very large secondary cache as a victim cache, to avoid duplicate storage of the contents of the large primary cache

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AKA BOTH AMD AND INTEL USE VICTIM CACHE AND THEY BOTH USE PREFETCHING. To assume AMD doesn't is just plan retarded :stick:

Quote:

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Originally Posted by red

Please tell us more..about everything Dave:D

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wish I could....but early signs are good.

dave

Quote:

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Originally Posted by Serge84

http://xs208.xs.to/xs208/06442/CONROE-L-NOR.JPG 512kb Stock
http://forum.pcstats.com/showthread.php?t=37608 VS 4mb Stock
http://xs208.xs.to/xs208/06442/266-pi1m.JPG VS 4mb 3.1ghz

This proves conroe is cache dependent and since this is a single threated benchmark the difference between having 2 cores and one in Super pi doesn't exist. A single core AMD scores the same in super PI just as a dual core does because only one core is used so this supports my statment super pi and conroe are made for eachother. With out the cache conroe would be no better then K8's arc wise. The rest is just a gimmic. Its real performance comes from having a insane amount of cache. In the real world it means nothing why AMD's act the same as conroes in performance because most can't tell or see the difference. Conroe was made to bench and its performance doesn't exist in the real world like its hyped in benchmarks because the cache is the main reason for such high scores in super pi but isn't reflected in every benchmark for a reason. Its also not reflected in the real world because most programs will not use all of the cache in the same way the benches do it was made for. In the real world the benches just don't add up for standard use as a system your just not going to see it in everyday things you do. Specially because of the FSB limit.

K8L may use this in a similar way to get more performance by loading stuff way before its calculated with the help of L3 like conroe's large cache size K8L may feel much faster because it uses this trick to make itself feel faster by processing something far ahead of time wile its already loaded into cache afterwords. The more cache you have at this level usouly makes a big difference in performance but not the case with AMD in the past with K8's. Yet I beleave the cache may effect K8L more like Conroe does since its similar with large sizes of cache. Having L3 should make it feel much faster yet I could be wrong because it could be similar to K8's in that way and cache may not matter at all. But hyper transport would accelerate this effect it may help. If intel could do hyper transport then AMD would be in trouble. But since CSI will never come out before HT4 they don't have a chance in hell with FSB agenst K8L until 2009 with CSI-2. By then K11 will be out on 45nm going to 32nm with SOI-4 and 5.

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ROFLMAO!!! Those are some very entertaining theories! :clap:

Quote:

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Originally Posted by Serge84

http://xs208.xs.to/xs208/06442/CONROE-L-NOR.JPG 512kb Stock
http://forum.pcstats.com/showthread.php?t=37608 VS 4mb Stock
http://xs208.xs.to/xs208/06442/266-pi1m.JPG VS 4mb 3.1ghz

This proves conroe is cache dependent and since this is a single threated benchmark the difference between having 2 cores and one in Super pi doesn't exist. A single core AMD scores the same in super PI just as a dual core does because only one core is used so this supports my statment super pi and conroe are made for eachother. With out the cache conroe would be no better then K8's arc wise. The rest is just a gimmic. Its real performance comes from having a insane amount of cache. In the real world it means nothing why AMD's act the same as conroes in performance because most can't tell or see the difference. Conroe was made to bench and its performance doesn't exist in the real world like its hyped in benchmarks because the cache is the main reason for such high scores in super pi but isn't reflected in every benchmark for a reason. Its also not reflected in the real world because most programs will not use all of the cache in the same way the benches do it was made for. In the real world the benches just don't add up for standard use as a system your just not going to see it in everyday things you do. Specially because of the FSB limit.

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It's called shared cache moron. Conroe can used caches from both cores in single threaded apps.

So what if Conroe uses cache to beat AMD? It's the end performance that matters.

Americans used better weaponry to defeat Iraq - although I bet if you limit them to fist fights the Iraqis will fare a lot better. :rolleyes: ;)

And FYI, real world Conroe performance is a heck of a lot better than what AMD can muster atm. I really don't know who you're trying to kid here. I'm aware it's the AMD forums but I suggest you go back to the [H] n00bs with your wingman duby229 if you wish to sprout such fanboy BS.

You already got owned enough in the FX 55 vs E6300 thread and now you come back for more? Incredible.

K8's L2 cache doesn't prefetch data because it is a Victim Cache.
If a L2 cache miss occours data is loaded from RAM to L1 cache, so some data from cache L1 is evicted to L2.
L1 cache can prefetch data from L2.

Conroe's L2 cache cannot be Victim Cache cause it is Inclusive (includes a copy os L1 data).
Conroe's L2 cache can prefetch data from RAM!

dave_graham, AMD stated that 65nm K8 will be <= 2.6GHz
http://www.planet3dnow.de/cgi-bin/ne...?id=1159444771
If they are making 3GHz 65nm K8s, 65nm process is going very well.

Quote:

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Originally Posted by Epsilon84

It's called shared cache moron. Conroe can used caches from both cores in single threaded apps.

So what if Conroe uses cache to beat AMD? It's the end performance that matters.

Americans used better weaponry to defeat Iraq - although I bet if you limit them to fist fights the Iraqis will fare a lot better. :rolleyes: ;)

And FYI, real world Conroe performance is a heck of a lot better than what AMD can muster atm. I really don't know who you're trying to kid here. I'm aware it's the AMD forums but I suggest you go back to the [H] n00bs with your wingman duby229 if you wish to sprout such fanboy BS.

You already got owned enough in the FX 55 vs E6300 thread and now you come back for more? Incredible.

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Don't be too harsh on Serge or the Ghost, they are die hard AMD fans. Next thing you know, they will dream up some good theories and say 90nm A64X2 runs faster than 65nm Conroe.

BTW, still no benchies for 65nm A64X2s? :o

As doompc mentioned, the shared, big cache on Core2 is much more valuable than a normal shared cache of the same size.

Normally a big cache is almost useless for reading of new data. But Core2's L2 cache has speculative prefetch, which means it can get cache lines before confirming they are actually what is needed. If they turn out wrong it can discard them. The K8 cannot do this and I didn't hear anything that would indicate that this will happen. As a result, a K8 cache can only fetch lines very late after the CPU can proof that no further instructions will change the requirement for that particular cache line.

Quote:

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Originally Posted by uOpt

As doompc mentioned, the shared, big cache on Core2 is much more valuable than a normal shared cache of the same size.

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Do you have a degree in logic and we don't know ? :slap:

Quote:

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Normally a big cache is almost useless for reading of new data.

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wtf are u smoking ?!

Quote:

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But Core2's L2 cache has speculative prefetch, which means it can get cache lines before confirming they are actually what is needed. If they turn out wrong it can discard them. The K8 cannot do this and I didn't hear anything that would indicate that this will happen. As a result, a K8 cache can only fetch lines very late after the CPU can proof that no further instructions will change the requirement for that particular cache line.

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It boils down to Intel's prefetcher being more advanced than in the K8.This is due to the P4 , which had a prefetcher far better than anything else ( we might say it needed it with such lentghty pipelines ).Prescott stepped up the level and Conroe simply builds on that.

Whats with the sudden influx of newbies with these condescending attitudes? Is it really so hard to simply have a thread without all these :banana::banana::banana::banana: fits? There is possibly seven pages total of people flame baiting and biting at it.

I got a feeling here soon the Ban Hammer of Fuggality is gonna get brought down against some newblet heads, and an otherwise thread of decent information is going to get closed.

Incase you didn't get the memo.

And Dave, do keep us updated. Its greatly appreciated. Good info.

Quote:

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Originally Posted by Reznik Akime

Whats with the sudden influx of newbies with these condescending attitudes? Is it really so hard to simply have a thread without all these :banana::banana::banana::banana: fits? There is possibly seven pages total of people flame baiting and biting at it.

I got a feeling here soon the Ban Hammer of Fuggality is gonna get brought down against some newblet heads, and an otherwise thread of decent information is going to get closed.

Incase you didn't get the memo.

And Dave, do keep us updated. Its greatly appreciated. Good info.

---

:clap:

This msut be one of the worst threads in all XS, it's a shame that people cant give eachother anything because they are all the uber know-it-alls.

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http://www.dicofr.com/def2/image/spam.gif

Quote:

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Originally Posted by nn_step

http://www.dicofr.com/def2/image/spam.gif

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roger that.

so...let me get this straight. Rev.G will use SiGe?

which Stepping of Rev G?
Because the first few No
a Couple later ones Yes

Quote:

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Originally Posted by Epsilon84

It's called shared cache moron. Conroe can used caches from both cores in single threaded apps.

So what if Conroe uses cache to beat AMD? It's the end performance that matters.

Americans used better weaponry to defeat Iraq - although I bet if you limit them to fist fights the Iraqis will fare a lot better. :rolleyes: ;)

And FYI, real world Conroe performance is a heck of a lot better than what AMD can muster atm. I really don't know who you're trying to kid here. I'm aware it's the AMD forums but I suggest you go back to the [H] n00bs with your wingman duby229 if you wish to sprout such fanboy BS.

You already got owned enough in the FX 55 vs E6300 thread and now you come back for more? Incredible.

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Why call a bloke a moron, just because you disagree with him.

I think your post shows your level of maturity.

Grow up please.

Sometimes you have to speak the truth...being polite when arguing with an idiot is making him an unnecessary favour.