Q9650 @ 4.3ghz 4 X 1gb @ Ddr1148
4.3GHz was still running when I got hack from the Pub :toast2: so here's the settings I used.
As I mentioned earlier the VTT, VNB are a good few clicks over what was needed but I was concentration on getting 4 x 1gb sticks to run with low voltage rather than nailing an overall low voltage clock.
The vcore is also a few clicks higher than it needs to be as I tested it with ITB/Linpack after getting the rig CPU stable with Prime custom runs. I found IBT/Linpack needed the extra voltage to complete successfully.
I think 4.3GHz could be on the edge of stability judging by the way the Primes worker threads wandered during this loop. I will play about with 4.3GHz to see if I can get the threads to run more even & post my findings if I work it out.
I'll add some Everest (about 10200mbs across the board & 50ns from memory), 3D & anything else anybody wants to see to this post as soon as I get some free time, I got to wine & dine my good lady tonight & I'm working all weekend again!!!
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http://i106.photobucket.com/albums/m...1148/95HGO.jpg
Code:
>CPU Feature:
Thermal Management Control.......... - Disabled
PPM(EIST) Mode...................... - Disabled
Limit CPUID MaxVal.................. - Disabled
CIE Function........................ - Disabled
Execute Disable Bit................. - Enabled
Virtualization Technology........... - Enabled
Core Multi-Processing............... - Enabled
>DRAM Timing:
Enhance Data transmitting........... - Fast
Enhance Addressing.................. - Fast
T2 Dispatch......................... - Auto
>Clock Setting Fine Delay Press Enter:
DLL And RCOMP Settings.............. - By Menu
Ch1 Dram Defaul Skew................ - Model 6
Ch2 Dram Defaul Skew................ - Model 6
RCOMP Settings...................... - Model 1
Fine Delay Step Degree.............. - 100ps
Ch1 Clock Crossing Setting.......... - More Aggressive
DIMM1 Clock Fine Delay.............. - Current[2074ps]
DIMM2 Clock Fine Delay.............. - Current[2074ps]
Ch1 Control0 Fine Delay............. - Current[454ps]
Ch1 Control1 Fine Delay............. - Current[454ps]
Ch1 Control2 Fine Delay............. - Current[386ps]
Ch1 Control3 Fine Delay............. - Current[372ps]
Ch1 Command Fine Delay.............. - Current[454ps]
Ch2 Clock Crossing Setting.......... - More Aggressive
DIMM3 Clock Fine Delay.............. - Current[2088ps]
DIMM4 Clock Fine Delay.............. - Current[2088ps]
Ch2 Control0 Fine Delay............. - Current[426ps]
Ch2 Control1 Fine Delay............. - Current[426ps]
Ch2 Control2 Fine Delay............. - Current[330ps]
Ch2 Control3 Fine Delay............. - Current[316ps]
Ch2 Command Fine Delay.............. - Current[426ps]
Ch1 Ch2 Common Clock Setting........ - More Aggressive
Ch1 RDCAS GNT-Chip Delay............ - Auto
Ch1 WRCAS GNT-Chip Delay............ - Auto
Ch1 Command To CS Delay............. - Auto
.
Ch2 RDCAS GNT-Chip Delay............ - Auto
Ch2 WRCAS GNT-Chip Delay............ - Auto
Ch2 Command To CS Delay............. - Auto
Flex Memory Mode..................... - Auto
CAS Latency Time (tCL)............... - 5
RAS# to CAS# Delay (tRCD)............ - 5
RAS# Precharge (tRP)................. - 5
Precharge Delay (tRAS)............... - 10
All Precharge to Act................. - 5
REF to ACT Delay (tRFC).............. - 30
Performance Level.................... - Auto
>Read delay phase adjust Press Enter:
Channel 1 Phase 0 Pull-In........... - Auto
Channel 1 Phase 1 Pull-In........... - Auto
Channel 1 Phase 2 Pull-In........... - Auto
Channel 1 Phase 3 Pull-In........... - Auto
Channel 1 Phase 4 Pull-In........... - Auto
Channel 2 Phase 0 Pull-In........... - Auto
Channel 2 Phase 1 Pull-In........... - Auto
Channel 2 Phase 2 Pull-In........... - Auto
Channel 2 Phase 3 Pull-In........... - Auto
Channel 2 Phase 4 Pull-In........... - Auto
Write to PRE Delay (tWR)............ - 13
Rank Write to Read (tWTR)........... - 11
ACT to ACT Delay (tRRD)............. - 3
Read to Write Delay (tRDWR)......... - 8
Ranks Write to Write (tWRWR)........ - Auto
Ranks Read to Read (tRDRD).......... - Auto
Ranks Write to Read (tWRRD)......... - Auto
ALL PRE to Refresh.................. - Auto
>Voltage Settings:
CPU VID Control..................... - 1.4625V
CPU VID Special Add................. - Enabled
CPU VID Special Add................. - Auto
DRAM Voltage Control................ - 2.01v
SB Core/CPU PLL Voltage............. - 1.55v
NB Core Voltage..................... - 1.455v
CPU VTT Voltage..................... - 1.398v
Vcore Droop Control................. - Disabled
Clockgen Voltage Control............ - 3.60v
GTL+ Buffer Strength................ - Weak
CPU GTL 0 REF Volt.................. - 0.6700
CPU GTL 2 REF Volt.................. - 0.6700
CPU GTL 1 REF Volt.................. - 0.6700
CPU GTL 3 REF Volt.................. - 0.6700
North Bridge GTL 0 REF Volt......... - 0.6900
North Bridge GTL 1 REF Volt......... - 0.6900
FSB Vref............................ - Auto
Genie BIOS Settings:
Exist Setup Shutdown................ - Mode 2
Exist Shutdown After AC loss........ - Disabled
AC Shutdown Free.................... - Disabled
O.C Clock Fail Retry Counter........ - 0
O.C Clock Fail CMOS Reloaded........ - Disabled
CPU Clock Ratio..................... - 9
Target CPU Clock.................... - 4302MHz
CPU Clock........................... - 478
Boot Up Clock....................... - 400
CPU Clock Amplitude................. - 1000mV
CPU Clock0 Skew..................... - 0ps
CPU Clock1 Skew..................... - 0ps
DRAM Speed.......................... - 333/800
Target DRAM Speed................... - 1148MHz
PCIE Clock.......................... - 105mhz
PCIE Slot Config.................... - 1x 1x
CPU Spread Spectrum................. - Disabled
PCIE Spread Spectrum................ - Disabled
Short Description:
Q9650 @ 4.3GHz 1.375v (CPU-Z Load)
4 x 1GB RAM @ DDR1148 2.01v BIOS, 2.05v Actual (DMM)