Think more with transistor count. I estimate, depending on the exact die size but assuming around 440mm2, around 5.5b-6b.
512b is possible by using a
more area efficient PHY like in Bonaire/Pitcairn but lower speed would easily give +300Gbps of bandwidth while decreasing the area of the PHY by a third or about 66% the size of Tahiti's total PHY. There is also the comment that Stilt made about a rectangular die which suggests they are looking to maximize the perimeter.
We already know that Hawaii has a more complex PCB than Tahiti, more layers, so that could hint at either faster memory speeds(7Gbps) or a larger bus(512b) or just more power.